Order this document
by MCM6706CR/D
SEMICONDUCTOR TECHNICAL DATA
MCM6706CR
Product Preview
32K x 8 Bit Static Random
Access Memory
The MCM6706CR is a 262,144 bit static random access memory organized
as 32,768 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.
J PACKAGE
300 MIL SOJ
CASE 857–02
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706CR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
PIN ASSIGNMENT
A
A
A
A
NC
A
1
32
31
30
29
28
27
•
•
•
•
•
Single 5.0 V ± 10% Power Supply
2
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706CR–5 = 5 ns
MCM6706CR–5.5 = 5.5 ns
A
3
A
4
G
E
DQ
DQ
5
DQ
DQ
V
6
•
Center Power and I/O Pins for Reduced Noise
7
26
25
24
23
22
21
20
V
8
CC
SS
BLOCK DIAGRAM
V
V
CC
9
SS
A
A
A
V
V
DQ
DQ
DQ
A
10
11
12
13
14
CC
SS
DQ
W
A
A
MEMORY
A
ROW
DECODER
MATRIX
512 ROWS x 64 x 8
COLUMNS
A
A
A
A
A
A
A
A
A
19
18
17
A
15
16
NC
DQ0
PIN NAMES
COLUMN I/O
INPUT
DATA
CONTROL
COLUMN DECODER
A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . . . . . Data Input/Output
DQ7
E
A
A
A
A
A
A
V
V
. . . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
NC . . . . . . . . . . . . . . . . . . . . . . No Connection
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
Motorola, Inc. 1996
MOTOROLA FAST SRAM
MCM6706CR
1