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MCM64Z836TQ166 PDF预览

MCM64Z836TQ166

更新时间: 2024-11-19 10:07:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器内存集成电路
页数 文件大小 规格书
31页 356K
描述
ZBT SRAM, 256KX36, 3.6ns, CMOS, PQFP100, TQFP-100

MCM64Z836TQ166 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:LQFP,Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.85最长访问时间:3.6 ns
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:9437184 bit
内存集成电路类型:ZBT SRAM内存宽度:36
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX36
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MCM64Z836TQ166 数据手册

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Order this document  
by MCM64Z836/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM64Z836  
MCM64Z918  
Product Proposal  
256K x 36 and 512K x 18  
Bit Pipelined ZBT RAM  
Synchronous Fast Static RAM  
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide  
Zero Bus Turnaround . The ZBT RAM allows 100% use of bus cycles during  
back–to–back read/write and write/read cycles. The MCM64Z836 (organized as  
256K words by 36 bits) and the MCM64Z918 (organized as 512K words by 18  
bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-  
nology. This device integrates input registers, an output register, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in communication applications. Synchronous design allows precise cycle  
control with the use of an external positive–edge–triggered clock (CK). CMOS  
circuitry reduces the overall power consumption of the integrated functions for  
greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQ), and all control signals except output enable  
(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled  
through positive–edge–triggered noninverting registers.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (CK) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Forreadcycles, pipelinedSRAMoutputdataistemporarilystoredbyanedge–  
triggered output register and then released to the output buffers at the next rising  
edge of clock (CK).  
2.5 V LVTTL and LVCMOS Compatible  
MCM64Z836/918–225 = 2.6 ns Access/4.4 ns Cycle (225 MHz)  
MCM64Z836/918–200 = 3.2 ns Access/5 ns Cycle (200 MHz)  
MCM64Z836/918–166 = 3.6 ns Access/6 ns Cycle (166 MHz)  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Sleep Mode (ZZ)  
Two–Cycle Deselect  
Byte Write Control  
ADV Controlled Burst  
IEEE 1149–1 Sample Only JTAG  
100–Pin TQFP and 119–Bump PBGA Packages  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by  
Micron Technology, Inc. and Motorola, Inc.  
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 2  
6/2/99  
Motorola, Inc. 1999  

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