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MCM63Z919TQ8.5R PDF预览

MCM63Z919TQ8.5R

更新时间: 2024-11-20 14:43:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器内存集成电路
页数 文件大小 规格书
32页 358K
描述
512KX18 ZBT SRAM, 8.5ns, PQFP100, TQFP-100

MCM63Z919TQ8.5R 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92Is Samacsys:N
最长访问时间:8.5 nsJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:9437184 bit内存集成电路类型:ZBT SRAM
内存宽度:18功能数量:1
端子数量:100字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX18封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

MCM63Z919TQ8.5R 数据手册

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Order this document  
by MCM63Z837/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63Z837  
MCM63Z919  
Advance Information  
256K x 36 and 512K x 18 Bit  
Flow–Through ZBT RAM  
Synchronous Fast Static RAM  
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide  
Zero Bus Turnaround . The ZBT RAM allows 100% use of bus cycles during  
back–to–back read/write and write/read cycles. The MCM63Z837 (organized as  
256K words by 36 bits) and the MCM63Z919 (organized as 512K words by 18  
bits) are fabricated in Motorola’s high performance silicon gate CMOS  
technology. This device integrates input registers, a 2–bit address counter, and  
high speed SRAM onto a single monolithic circuit for reduced parts count in  
communication applications. Synchronous design allows precise cycle control  
with the use of an external clock (CK). CMOS circuitry reduces the overall power  
consumption of the integrated functions for greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQ), and all control signals except output enable  
(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled  
through positive–edge–triggered noninverting registers.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (CK) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
3.3 V LVTTL and LVCMOS Compatible  
MCM63Z837/918–7.0 = 7 ns Access/8.5 ns Cycle (117 MHz)  
MCM63Z837/918–7.5 = 7.5 ns Access/10 ns Cycle (100 MHz)  
MCM63Z837/918–8 = 8 ns Access/10.5 ns Cycle (95 MHz)  
MCM63Z837/918–8.5 = 8.5 ns Access/11 ns Cycle (90 MHz)  
MCM63Z837/918–10 = 10 ns Access/15 ns Cycle (66 MHz)  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Sleep Mode (ZZ)  
Single–Cycle Deselect  
Byte Write Control  
ADV Controlled Burst  
IEEE 1149–1 Sample Only JTAG  
100–Pin TQFP and 119–Bump PBGA Packages  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by  
Micron Technology, Inc. and Motorola, Inc.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
6/3/99  
Motorola, Inc. 1999  

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