Datasheet > MCM63Z836TQ200

MCM63Z836TQ200

更新时间： 2024-11-26 04:38:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器
页数	文件大小	规格书
32页	355K
描述
ZBT SRAM, 256KX36, 3ns, CMOS, PQFP100, TQFP-100

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MCM63Z836TQ200 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM63Z836

MCM63Z918

Product Proposal

256K x 36 and 512K x 18

Bit Pipelined ZBT RAM

Synchronous Fast Static RAM

The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide

Zero Bus Turnaround . The ZBT RAM allows 100% use of bus cycles during

back–to–back read/write and write/read cycles. The MCM63Z836 (organized as

256K words by 36 bits) and the MCM63Z918 (organized as 512K words by 18

bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-

nology. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in communication applications. Synchronous design allows precise cycle

control with the use of an external positive–edge–triggered clock (CK). CMOS

circuitry reduces the overall power consumption of the integrated functions for

greater reliability.

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled

through positive–edge–triggered noninverting registers.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (CK) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Forreadcycles, pipelinedSRAMoutputdataistemporarilystoredbyanedge–

triggered output register and then released to the output buffers at the next rising

edge of clock (CK).

•

3.3 V Core, 3.3 V LVTTL and LVCMOS Compatible I/O Supply

MCM63Z836/918–225 = 2.6 ns Access/4.4 ns Cycle (225 MHz)

MCM63Z836/918–200 = 3.2 ns Access/5 ns Cycle (200 MHz)

MCM63Z836/918–166 = 3.6 ns Access/6 ns Cycle (166 MHz)

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Sleep Mode (ZZ)

Two–Cycle Deselect

Byte Write Control

ADV Controlled Burst

•

IEEE 1149–1 Sample Only JTAG

100–Pin TQFP and 119–Bump PBGA Packages

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1

6/2/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63Z836•MCM63Z918

12 3 4 5 6 7...32

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与MCM63Z836TQ200相关器件

型号	品牌	获取价格	描述	数据表
MCM63Z836TQ200R	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 3ns, CMOS, PQFP100, TQFP-100
MCM63Z836TQ225	MOTOROLA	获取价格	256KX36 ZBT SRAM, 2.6ns, PQFP100, TQFP-100
MCM63Z836TQ225R	MOTOROLA	获取价格	256KX36 ZBT SRAM, 2.6ns, PQFP100, TQFP-100
MCM63Z836TQ7	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM63Z836TQ7	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 7ns, CMOS, PQFP100, TQFP-100
MCM63Z836TQ7R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM63Z836TQ7R	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 7ns, CMOS, PQFP100, TQFP-100
MCM63Z836TQ8	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM63Z836TQ8	MOTOROLA	获取价格	256KX36 ZBT SRAM, 8ns, PQFP100, TQFP-100
MCM63Z836TQ8.5	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 8.5ns, CMOS, PQFP100, TQFP-100

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