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MCM62X308J17 PDF预览

MCM62X308J17

更新时间: 2024-09-25 19:48:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器光电二极管输出元件内存集成电路
页数 文件大小 规格书
20页 284K
描述
Dual-Port SRAM, 8KX8, 17ns, MOS, PDSO28, 0.300 INCH, SOJ-28

MCM62X308J17 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOJ,Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.92最长访问时间:17 ns
其他特性:PROGRAMMABLE OUTPUT ENABLEJESD-30 代码:R-PDSO-J28
JESD-609代码:e0长度:18.42 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端口数量:2端子数量:28
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.76 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MCM62X308J17 数据手册

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Order this document  
by MCM62X308/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM62X308  
Synchronous Line Buffer:  
8K x 8 Bit Fast Static Dual  
Ported Memory  
With IEEE Standard 1149.1 Test Access Port  
and Boundary–Scan (JTAG)  
28  
J PACKAGE  
300 MIL SOJ  
CASE 810B–03  
1
The MCM62X308 is a synchronous, dual ported memory organized as 8,192  
words of 8 bits each, fabricated using Motorola’s double–metal, double–poly,  
0.65 µm CMOS process. It is intended for high speed video or other applications  
which process data on a line–by–line basis. Through the use of a single clock and  
port control inputs, separate read and write data ports provide simultaneous ac-  
cess to a common memory array. Simultaneous read/write access to the same  
address location is also allowed, with old data being read followed by a write of  
the new data. This allows multiple devices to be cascaded with the output of one  
directly driving the input of another. In this configuration the data stream can be  
tapped at strategic interconnect points to perform various digital filtering functions.  
Since there are no external address inputs, separate internal read and write ad-  
dress counters are provided as a means of indexing the memory array. These  
counters are preloaded and then selectively incremented or decremented by as-  
serting read enable (RE) and write enable (WE) inputs, allowing cycle to cycle  
control. The address counters can be reloaded back to their initial values through  
the use of the read reload (RR) and write reload (WR) control inputs. These inputs  
initiate the transfer of address reload register values into the address counters  
which index the memory array. When an address counter reaches 0000 (on down  
count) or FFFF (on up count), it will roll over on the next count. The TDI input is  
used to write the reload registers using special test access port instructions.  
The read and write address counters are 16 bits long, and only 13 of the 16 bits  
are required to index the 8K deep memory array. The remaining three bits are  
used for depth expansion. These three bits are compared to the lower three bits  
in the control register, and as long as they are equal that port (i.e., read or write)  
will remain active. If the bits do not compare, the port will become inactive (i.e.,  
for read outputs, high–z; for write inputs, disabled) however, the counter will con-  
tinue to count on the rising edge of K as long as the port enable signal (RE or WE)  
is asserted. The TDI input is used to write the control register using special test  
access port instructions.  
PIN ASSIGNMENT  
D7  
D6  
1
2
28  
27  
Q7  
Q6  
D5  
D4  
D3  
D2  
D1  
D0  
3
26  
25  
24  
23  
22  
21  
20  
19  
18  
Q5  
Q4  
Q3  
Q2  
Q1  
Q0  
4
5
6
7
8
V
9
V
SS  
DD  
K
10  
G
WE 11  
WR 12  
TDI 13  
RE  
RR  
17  
16  
15  
TDO  
TMS  
TCK 14  
PIN NAMES  
The output enable Input can be programmed to be either synchronous or  
asynchronous through the control register.  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input  
WE . . . . . . . . . . . . . . . . . . . Write Enable Input  
WR . . . . . . . . . . . Write Address Reload Input  
RE . . . . . . . . . . . . . . . . . . .Read Enable Input  
RR . . . . . . . . . . . Read Address Reload Input  
G . . . . . . . . . . . . . . . . . . . Output Enable Input  
D0 – D7 . . . . . . . . . . . . . . . . . . . . . Data Inputs  
Q0 – Q7 . . . . . . . . . . . . . . . . . . . . Data Outputs  
TCK . . . . . . . . . . . . . . . . . . . . Test Clock Input  
TMS . . . . . . . . . . . . . . . . . . . Test Mode Select  
TDI . . . . . . . . . . . . . . . . . . . . . . Test Data Input  
TDO . . . . . . . . . . . . . . . . . . . Test Data Output  
The MCM62X308 is available in a 28 pin SOJ package.  
8K x 8 Fast Access Static Memory Array  
Single 5 V Power Supply — MCM62X308–15–5: ± 5%  
MCM62X308–17: ± 10%  
Synchronous, Simultaneous Read/Write Memory Access  
50 MHz Maximum Clock Cycle Time, < 15 ns Read Access  
Single Clock Operation  
Separate Read/Write Address Counters with Reload Control  
Separate Up/Down Counter Control for Both Read and Write  
Programmable Output Enable Control (Synchronous or Asynchronous)  
Cascadable I/O Interface  
IEEE Standard 1149.1 Test Port (JTAG)  
Expand ID Register for Depth Expansion  
High Board Density SOJ Package  
V
DD  
V
SS  
. . . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
Fully TTL Compatible  
REV 1  
5/95  
Motorola, Inc. 1994  

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