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MCM54260BJ70 PDF预览

MCM54260BJ70

更新时间: 2024-11-21 20:10:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
32页 723K
描述
Fast Page DRAM, 256KX16, 70ns, CMOS, PDSO40, 0.400 INCH, SOJ-40

MCM54260BJ70 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:0.400 INCH, SOJ-40Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.85Is Samacsys:N
访问模式:FAST PAGE最长访问时间:70 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-J40JESD-609代码:e0
长度:26.035 mm内存密度:4194304 bit
内存集成电路类型:FAST PAGE DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:40字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ40,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
刷新周期:512座面最大高度:3.76 mm
自我刷新:NO最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

MCM54260BJ70 数据手册

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Order this document  
by MCM54260B/D  
SEMICONDUCTOR  
TECHNICAL DATA  
MCM54260B  
MCM5L4260B  
MCM5S4260B  
Advance Information  
256K x 16 CMOS Dynamic RAM  
Fast Page Mode – 2 CAS, 1 Write Enable  
The MCM54260B is a 0.6µ CMOS high–speed dynamic random access memory.  
It is organized as 262,144 sixteen–bit words and fabricated with CMOS silicon–gate  
process technology. Advanced circuit design and fine line processing provide high  
performance, improved reliability, and low cost.  
The MCM54260B requires only 9 address lines; row and column address inputs  
are multiplexed. The device is packaged in a standard 400 mil SOJ plastic package  
and a 400 mil thin–small–outline package (TSOP).  
J PACKAGE  
400 MIL SOJ  
CASE 923A–01  
Three–State Data Output  
Fast Page Mode  
TTL–Compatible Inputs and Outputs  
RAS–Only Refresh  
CAS Before RAS Refresh  
Hidden Refresh  
512 Cycle Refresh:  
T PACKAGE  
400 MIL TSOP  
CASE 924–01  
PIN NAMES  
MCM54260B = 8 ms  
MCM5L4260B = 64 ms  
MCM5S4260B = 64 ms  
A0 – A8 . . . . . . . . . . . . . . Address Inputs  
DQ0 – DQ15 . . . . . . . Data Input/Output  
W . . . . . . . . . . . . . . . . Read/Write Enable  
RAS . . . . . . . . . . . . Row Address Strobe  
LCAS, UCAS . Column Address Strobe  
Fast Access Time (t ):  
RAC  
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70 = 70 ns (Max)  
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80 = 80 ns (Max)  
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10 = 100 ns (Max)  
Low Active Power Dissipation:  
V
CC  
V
SS  
. . . . . . . . . . . Power Supply (+ 5 V)  
. . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connect  
G . . . . . . . . . . . . . . . . . . . Output Enable  
MCM54260B–70, MCM5L4260B–70, and MCM5S4260B–70 = 550 mW (Max)  
MCM54260B–80, MCM5L4260B–80, and MCM5S4260B–80 = 468 mW (Max)  
MCM54260B–10, MCM5L4260B–10, and MCM5S4260B–10 = 413 mW (Max)  
Low Standby Power Dissipation:  
MCM54260B, MCM5L4260B, and MCM5S4260B= 5.5 mW (Max, TTL Levels)  
Battery Backup Power Dissipation:  
MCM5L4260B and MCM5S4260B = 1.7 mW (Max, Battery Backup Mode,  
t
= 125 µs)  
RC  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 3  
10/95  
Motorola, Inc. 1995  

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Fast Page DRAM, 256KX16, 70ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40
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256KX16 FAST PAGE DRAM, 100ns, PZIP40, 0.475 INCH, 2.54 MM PITCH, ZIP-40
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Fast Page DRAM, 256KX16, 70ns, CMOS, PZIP40, 0.475 INCH, 2.54 MM PITCH, ZIP-40