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MCF5483CVR166 PDF预览

MCF5483CVR166

更新时间: 2024-09-28 15:41:07
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
34页 537K
描述
MCF548X V4ECORE MMU, FPU

MCF5483CVR166 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:27 X 27 MM, 1 MM PITCH, MS-034AAL-1, PBGA-388针数:388
Reach Compliance Code:unknownECCN代码:5A002
HTS代码:8542.31.00.01风险等级:5.55
位大小:32边界扫描:YES
最大时钟频率:66.67 MHz格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-PBGA-B388
JESD-609代码:e1长度:27 mm
低功率模式:YES湿度敏感等级:3
端子数量:388最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA388,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260电源:1.5,2.5,3.3 V
认证状态:Not Qualified座面最大高度:2.55 mm
速度:166.66 MHz子类别:Microprocessors
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:27 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

MCF5483CVR166 数据手册

 浏览型号MCF5483CVR166的Datasheet PDF文件第2页浏览型号MCF5483CVR166的Datasheet PDF文件第3页浏览型号MCF5483CVR166的Datasheet PDF文件第4页浏览型号MCF5483CVR166的Datasheet PDF文件第5页浏览型号MCF5483CVR166的Datasheet PDF文件第6页浏览型号MCF5483CVR166的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet  
Document Number: MCF5485EC  
Rev. 4, 12/2007  
MCF548x  
MCF548x ColdFire®  
Microprocessor  
TEPBGA–388  
27 mm x 27 mm  
Supports MCF5480, MCF5481,  
MCF5482, MCF5483, MCF5484, and  
MCF5485  
Features list:  
• ColdFire V4e Core  
endpoints, interrupt, bulk, or isochronous  
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte  
of endpoint descriptor RAM  
– Limited superscalar V4 ColdFire processor core  
– Up to 200MHz peak internal core frequency (308 MIPS  
[Dhrystone 2.1] @ 200 MHz)  
– Harvard architecture  
– 32-Kbyte instruction cache  
– Integrated physical layer interface  
– Up to four programmable serial controllers (PSCs) each  
with separate 512-byte receive and transmit FIFOs for  
UART, USART, modem, codec, and IrDA 1.1 interfaces  
2
– I C peripheral interface  
– 32-Kbyte data cache  
– Two FlexCAN controller area network 2.0B controllers  
each with 16 message buffers  
– DMA Serial Peripheral Interface (DSPI)  
• Optional Cryptography accelerator module  
– Execution units for:  
– Memory Management Unit (MMU)  
– Separate, 32-entry, fully-associative instruction and  
data translation lookahead buffers  
– Floating point unit (FPU)  
– Double-precision conforms to IEE-754 standard  
– Eight floating point registers  
– DES/3DES block cipher  
– AES block cipher  
– RC4 stream cipher  
– MD5/SHA-1/SHA-256/HMAC hashing  
– Random Number Generator  
• Internal master bus (XLB) arbiter  
– High performance split address and data transactions  
– Support for various parking modes  
• 32-bit double data rate (DDR) synchronous DRAM  
(SDRAM) controller  
• 32-Kbyte system SRAM  
– Arbitration mechanism shares bandwidth between  
internal bus masters  
– 66–133 MHz operation  
– Supports DDR and SDR DRAM  
• System integration unit (SIU)  
– Interrupt controller  
– Built-in initialization and refresh  
– Up to four chip selects enabling up to one GB of external  
memory  
– Watchdog timer  
– Two 32-bit slice timers alarm and interrupt generation  
– Up to four 32-bit general-purpose timers, compare, and  
PWM capability  
Version 2.2 peripheral component interconnect (PCI) bus  
– 32-bit target and initiator operation  
– Support for up to five external PCI masters  
– 33–66 MHz operation with PCI bus to XLB divider  
ratios of 1:1, 1:2, and 1:4  
– GPIO ports multiplexed with peripheral pins  
• Debug and test features  
– ColdFire background debug mode (BDM) port  
– JTAG/ IEEE 1149.1 test access port  
• PLL and clock generator  
• Flexible multi-function external bus (FlexBus)  
– Provides a glueless interface to boot flash/ROM,  
SRAM, and peripheral devices  
– 30 to 66.67 MHz input frequency range  
• Operating Voltages  
– Up to six chip selects  
– 33 – 66 MHz operation  
– 1.5V internal logic  
• Communications I/O subsystem  
– 2.5V DDR SDRAM bus I/O  
– 3.3V PCI, FlexBus, and all other I/O  
• Estimated power consumption  
– Less than 1.5W (388 PBGA)  
– Intelligent 16 channel DMA controller  
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)  
each with separate 2-Kbyte receive and transmit FIFOs  
– Universal serial bus (USB) version 2.0 device controller  
– Support for one control and six programmable  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  

MCF5483CVR166 替代型号

型号 品牌 替代类型 描述 数据表
MCF5483CZP166 NXP

类似代替

IC,MICROPROCESSOR,32-BIT,BGA,388PIN,PLASTIC

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