Datasheet > MC92053

MC92053

更新时间： 2024-09-24 22:46:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
6页	48K
描述
Quad FTTC Network Framer

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MC92053 数据手册

Order this Data Sheet by MC92053/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC92053

Product Brief

MC92053

Quad FTTC Network Framer

The MC92053 is a peripheral device composed of four parallel bidirectional TC-sublayer functional units with

UTOPIA Level 2 compliant ATM-layer ports.

MC92053 Features

•

Implements the DAVIC short-range baseband asymmetrical physical layer standard

Interfaces to an ATM-layer device using a multi-PHY UTOPIA Level 2 compliant interface

Provides an 8-bit system interface as a generic slave device

IEEE 1149.1 (JTAG) boundary scan test port

3.3 V operation with TTL compatibility on I/O pins

Extended temperature operation: -40 to 85 ^°C

Available in 208 Pin Plastic Quad Flat Package

Each of the four framers:

•

Provides a bit rate of up to 51.84 Mbit/sec downstream

Controls the TIme Division Multiple Access (TDMA) among up to 4 user devices

Supports a bit rate of up to 6.48 Mbit/s upstream, including DAVIC Bit Rates B, C, and D

Includes serial data link interfaces for upstream and downstream frames

Performs convolutional interleaving of the downstream payload blocks for the full range of interleaving

depths (M = 1-31) using an external 32K x 16 SRAM shared by all four framers

Performs Reed-Solomon encoding of the downstream frames and decoding of the upstream frames

Performs ATM cell TC functions, including HEC-based error detection and correction on the upstream data

Includes serial data interfaces to Physical Media Devices (PMD).

•

Framer #0

UTOPIA

I/F

Framer #1

Framer #2

UTOPIA

I/F

Framer #3

Microprocessor

JTAG Controller

Interface

Figure 1. MC92053 Block Diagram

This document contains information on a new product.

Speciﬁcations and information herein are subject to change without notice.

MOTOROLA, INC. 1997

12 3 4 5 6

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