Datasheet > MC84-74HC393

MC84-74HC393

更新时间： 2025-07-18 22:28:19

品牌	Logo	应用领域
安森美 - ONSEMI		计数器
页数	文件大小	规格书
7页	199K
描述
Dual 4-Stage Binary Ripple Counter

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中文翻译

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数据手册

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MC84-74HC393 数据手册

MC54/74HC393

PIN DESCRIPTIONS

INPUTS

vided for each counter. A high at the Reset input prevents

counting and forces all four outputs low.

Clock (Pins 1, 13)

Clock input. The internal flip–flops are toggled and the

counter state advances on high–to–low transitions of the

clock input.

OUTPUTS

CONTROL INPUTS

Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Reset (Pins 2, 12)

Active–high, asynchronous reset. A separate reset is pro-

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

90%

50%

RESET

50%

CLOCK

10%

GND

PHL

1/f

PLH

max

PHL

50%

rec

90%

50%

10%

50%

CLOCK

GND

THL

TLH

Figure 1.

Figure 2.

EXPANDED LOGIC DIAGRAM

TEST

POINT

1, 13

CLOCK

OUTPUT

3, 11

4, 10

DEVICE

UNDER

TEST

C *

* Includes all probe and jig capacitance

Figure 3. Test Circuit

5, 9

6, 8

2, 12

RESET

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

1 2 345 6 7

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