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MC74VHCT573A

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
7页 175K
描述
Octal D-Type Latch with 3-State Output

MC74VHCT573A 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHCT573A is an advanced high speed CMOS octal latch with  
3–state output fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
This 8–bit D–type latch is controlled by a latch enable input and an output  
enable input. When the output enable input is high, the eight outputs are in a  
high impedance state.  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
The VHCT inputs are compatible with TTL levels. This device can be used  
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS  
level output swings.  
The VHCT573A input and output (when disabled) structures provide  
protection when voltages between 0V and 5.5V are applied, regardless of  
the supply voltage. These input and output structures help prevent device  
destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
High Speed: t  
= 7.7ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Designed for 4.5V to 5.5V Operating Range  
IL IH  
ORDERING INFORMATION  
MC74VHCTXXXADW  
MC74VHCTXXXADT  
MC74VHCTXXXAM  
SOIC  
TSSOP  
SOIC EIAJ  
Low Noise: V  
= 1.6V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 234 FETs or 58.5 Equivalent Gates  
PIN ASSIGNMENT  
1
20  
V
OE  
D0  
D1  
CC  
LOGIC DIAGRAM  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
2
3
4
19  
18  
17  
D0  
D1  
D2  
Q0  
Q1  
Q2  
D2  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
Q4  
Q5  
Q6  
Q7  
6
5
6
16  
15  
NONINVERTING  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
Q3  
Q4  
D5  
7
7
8
14  
13  
D6  
8
D5  
D6  
D7  
Q5  
Q6  
Q7  
D7  
9
9
12  
GND  
10  
LE  
11  
1
LE  
OE  
FUNCTION TABLE  
INPUTS  
OUTPUT  
OE  
LE  
D
Q
L
L
L
H
H
L
H
L
X
X
H
L
No Change  
Z
H
X
6/97  
REV 0  
Motorola, Inc. 1997  

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