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MC74VHCT50ADR2G

更新时间: 2024-11-04 05:22:07
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安森美 - ONSEMI 转换器电平转换器
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描述
Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74VHCT50ADR2G 数据手册

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MC74VHCT50A  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHCT50A is a hex noninverting buffer fabricated with  
silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS  
low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffered  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic−level translator from  
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic  
to 3.0 V CMOS Logic while operating at the high−voltage power  
supply.  
14−LEAD SOIC  
D SUFFIX  
CASE 751A  
14−LEAD TSSOP  
DT SUFFIX  
CASE 948G  
The MC74VHCT50A input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V  
circuits. The output structures also provide protection when  
14−LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
V
= 0 V. These input and output structures help prevent device  
CC  
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
V
A6  
13  
Y6  
12  
A5  
11  
Y5  
10  
A4  
9
Y4  
8
CC  
14  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Pb−Free Packages are Available  
1
2
3
4
5
6
7
A1  
Y1  
A2  
Y2  
A3  
Y3 GND  
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
LOGIC DIAGRAM  
LOGIC SYMBOL  
1
3
5
2
FUNCTION TABLE  
A1  
A2  
A3  
Y1  
Y2  
Y3  
1
1
1
1
1
1
A1  
A2  
A3  
A4  
A5  
A6  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
A Input  
Y Output  
4
6
L
L
H
H
Y = A  
9
8
10  
12  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
A4  
A5  
A6  
Y4  
Y5  
Y6  
11  
13  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
January, 2007− Rev. 6  
MC74VHCT50A/D  

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