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MC74VHCT32A

更新时间: 2024-11-10 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器输入元件
页数 文件大小 规格书
8页 152K
描述
QUAD 2 INPUT OR GATE CMOS LOGIC LEVEL SHIFTER

MC74VHCT32A 数据手册

 浏览型号MC74VHCT32A的Datasheet PDF文件第2页浏览型号MC74VHCT32A的Datasheet PDF文件第3页浏览型号MC74VHCT32A的Datasheet PDF文件第4页浏览型号MC74VHCT32A的Datasheet PDF文件第5页浏览型号MC74VHCT32A的Datasheet PDF文件第6页浏览型号MC74VHCT32A的Datasheet PDF文件第7页 
with LSTTL–Compatible Inputs  
http://onsemi.com  
The MC74VHCT32A is an advanced high speed CMOS 2–input  
OR gate fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and  
the output has a full 5V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic–level translator from  
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to  
3.0V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHCT32A input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This  
allows the MC74VHCT32A to be used to interface 5V circuits to 3V  
14–LEAD SOIC  
D SUFFIX  
CASE 751A  
14–LEAD TSSOP  
DT SUFFIX  
CASE 948G  
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
circuits. The output structures also provide protection when V  
= 0V.  
PIN CONNECTION AND  
CC  
These input and output structures help prevent device destruction  
caused by supply voltage – input/output voltage mismatch, battery  
backup, hot insertion, etc.  
MARKING DIAGRAM (Top View)  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
14  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
A
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
IL IH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
Designed for 2V to 5.5V Operating Range  
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
FUNCTION TABLE  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Inputs  
Output  
Y
A
B
LOGIC DIAGRAM  
L
L
L
H
L
L
H
H
H
1
A1  
3
Y1  
Y2  
Y3  
2
4
5
H
H
B1  
A2  
B2  
H
6
8
Y = A  
B
9
A3  
B3  
ORDERING INFORMATION  
10  
Device  
Package  
SOIC  
Shipping  
12  
13  
A4  
B4  
11  
MC74VHCT32AD  
MC74VHCT32ADT  
MC74VHCT32AM  
55 Units/Rail  
96 Units/Rail  
50 Units/Rail  
Y4  
TSSOP  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
SOIC EIAJ  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
October, 1999 – Rev. 0.0  
MC74VHCT32A/D  

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