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MC74VHCT240ADW PDF预览

MC74VHCT240ADW

更新时间: 2024-11-19 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器
页数 文件大小 规格书
6页 172K
描述
Octal Bus Buffer/Line Driver

MC74VHCT240ADW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, TSSOP20,.25
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.24
控制类型:ENABLE LOW系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MC74VHCT240ADW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHCT240A is an advanced high speed CMOS octal bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The MC74VHCT240A is an inverting 3–state buffer, and has two  
active–low output enables. This device is designed to be used with 3–state  
memory address drivers, etc.  
The VHCT inputs are compatible with TTL levels. This device can be used  
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS  
level output swings.  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
The VHCT240A input and output (when disabled) structures provide  
protection when voltages between 0V and 5.5V are applied, regardless of  
the supply voltage. These input and output structures help prevent device  
destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
High Speed: t  
= 5.6ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Designed for 4.5V to 5.5V Operating Range  
IL IH  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
Low Noise: V  
= 1.1V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 110 FETs or 27.5 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCTXXXADW SOIC  
MC74VHCTXXXADT  
MC74VHCTXXXAM  
TSSOP  
SOIC EIAJ  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
OEA  
1
20  
V
CC  
A1  
YB4  
A2  
2
3
4
19  
18  
17  
OEB  
YA1  
B4  
YB3  
A3  
5
16  
15  
14  
13  
12  
11  
YA2  
B3  
DATA  
INVERTING  
OUTPUTS  
6
INPUTS  
11  
13  
9
7
YB2  
A4  
7
YA3  
B2  
B1  
B2  
YB1  
YB2  
8
YB1  
GND  
9
YA4  
B1  
10  
15  
17  
5
3
B3  
B4  
YB3  
YB4  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
YA, YB  
OEA, OEB  
A, B  
1
OEA  
OEB  
OUTPUT  
ENABLES  
L
L
H
L
H
X
H
L
Z
19  
6/97  
REV 0  
Motorola, Inc. 1997  

MC74VHCT240ADW 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHCT240ADWRG ONSEMI

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