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MC74VHC541MEL PDF预览

MC74VHC541MEL

更新时间: 2024-11-30 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 107K
描述
Octal Bus Buffer

MC74VHC541MEL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:EIAJ, SOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:5.275 mm
Base Number Matches:1

MC74VHC541MEL 数据手册

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MC74VHC541  
Octal Bus Buffer  
The MC74VHC541 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The MC74VHC541 is a noninverting type. When either OE1 or  
OE2 are high, the terminal outputs are in the high impedance state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
SOIC−20WB  
SUFFIX DW  
CASE 751D  
20  
20  
1
Features  
High Speed: t = 3.7ns (Typ) at V = 5.0 V  
PD  
CC  
TSSOP−20  
SUFFIX DT  
CASE 948E  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
1
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
SOEIAJ−20  
SUFFIX M  
CASE 967  
Designed for 2.0 V to 5.5 V Operating Range  
20  
Low Noise: V  
= 1.2 V (Max)  
OLP  
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
PIN ASSIGNMENT  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 134 FETs or 33.5 Equivalent Gates  
Pb−Free Packages are Available*  
OE1  
1
20  
V
CC  
A1  
A2  
A3  
2
3
4
19  
18  
17  
OE2  
Y1  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Y2  
A4  
A5  
A6  
A7  
A8  
5
6
7
8
9
16  
15  
14  
13  
12  
Y3  
Y4  
Y5  
Y6  
Y7  
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
GND 10  
11 Y8  
FUNCTION TABLE  
Inputs  
Output Y  
OE1 OE2  
A
A8  
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
1
OE1  
OUTPUT  
ENABLES  
19  
OE2  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
Figure 1. Logic Diagram  
dimensions section on page 4 of this data sheet.  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 4 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
April, 2006 − Rev. 5  
MC74VHC541/D  

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