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MC74VHC541DW PDF预览

MC74VHC541DW

更新时间: 2024-11-15 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 168K
描述
Octal Bus Buffer

MC74VHC541DW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.11Is Samacsys:N
控制类型:ENABLE LOW系列:AHC/VHC
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MC74VHC541DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC541 is an advanced high speed CMOS octal bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The MC74VHC541 is a noninverting type. When either OE1 or OE2 are  
high, the terminal outputs are in the high impedance state.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DW SUFFIX  
20–LEAD SOIC WIDE PACKAGE  
CASE 751D–04  
High Speed: t  
= 3.7ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIH  
NIL CC  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 1.2V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 134 FETs or 33.5 Equivalent Gates  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
LOGIC DIAGRAM  
ORDERING INFORMATION  
MC74VHCXXXDW  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC WIDE  
TSSOP  
SOIC EIAJ  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
PIN ASSIGNMENT  
OE1  
1
20  
V
CC  
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
A1  
A2  
A3  
2
3
4
19  
18  
17  
OE2  
Y1  
Y2  
A4  
A5  
5
16  
15  
14  
13  
12  
11  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
6
A6  
7
A8  
A7  
8
1
OE1  
A8  
9
OUTPUT  
ENABLES  
19  
GND  
10  
OE2  
FUNCTION TABLE  
Inputs  
Output Y  
OE1 OE2  
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
4/98  
REV 2  
Motorola, Inc. 1998  

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