SEMICONDUCTOR TECHNICAL DATA
The MC74VHC541 is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1 or OE2 are
high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–04
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High Speed: t
= 3.7ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
= V
= 28% V
NIH
NIL CC
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
Designed for 2V to 5.5V Operating Range
Low Noise: V
= 1.2V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
LOGIC DIAGRAM
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC WIDE
TSSOP
SOIC EIAJ
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
PIN ASSIGNMENT
OE1
1
20
V
CC
DATA
INPUTS
NONINVERTING
OUTPUTS
A1
A2
A3
2
3
4
19
18
17
OE2
Y1
Y2
A4
A5
5
16
15
14
13
12
11
Y3
Y4
Y5
Y6
Y7
Y8
6
A6
7
A8
A7
8
1
OE1
A8
9
OUTPUT
ENABLES
19
GND
10
OE2
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
4/98
REV 2
1
Motorola, Inc. 1998