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MC74VHC373DW PDF预览

MC74VHC373DW

更新时间: 2024-11-04 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 180K
描述
Octal D-Type Latch with 3-State Output

MC74VHC373DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.15系列:AHC/VHC
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MC74VHC373DW 数据手册

 浏览型号MC74VHC373DW的Datasheet PDF文件第2页浏览型号MC74VHC373DW的Datasheet PDF文件第3页浏览型号MC74VHC373DW的Datasheet PDF文件第4页浏览型号MC74VHC373DW的Datasheet PDF文件第5页浏览型号MC74VHC373DW的Datasheet PDF文件第6页浏览型号MC74VHC373DW的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC373 is an advanced high speed CMOS octal latch with  
3–state output fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
This 8–bit D–type latch is controlled by a latch enable input and an output  
enable input. When the output enable input is high, the eight outputs are in a  
high impedance state.  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
High Speed: t  
= 5.0ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIH  
NIL CC  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.9V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 186 FETs or 46.5 Equivalent Gates  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
ORDERING INFORMATION  
MC74VHCXXXDW  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
LOGIC DIAGRAM  
2
5
3
D0  
D1  
D2  
D3  
D4  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
4
PIN ASSIGNMENT  
6
7
1
20  
V
OE  
Q0  
D0  
D1  
CC  
8
9
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
2
3
4
19  
18  
17  
Q7  
D7  
D6  
13  
12  
15  
16  
19  
14  
17  
18  
D5  
D6  
D7  
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
Q5  
D5  
D4  
Q4  
6
D2  
7
11  
1
D3  
8
LE  
OE  
Q3  
9
GND  
10  
LE  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
OE  
LE  
D
L
L
L
H
H
L
H
L
X
X
H
L
No Change  
Z
H
X
6/97  
REV 1  
Motorola, Inc. 1997  

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