SEMICONDUCTOR TECHNICAL DATA
The MC74VHC244 is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC244 is a noninverting 3–state buffer, and has two
active–low output enables. This device is designed to be used with 3–state
memory address drivers, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
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High Speed: t
= 3.9ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
NIH
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
= V
= 28% V
NIL CC
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
Low Noise: V
= 0.9V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 136 FETs or 34 Equivalent Gates
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
LOGIC DIAGRAM
ORDERING INFORMATION
2
4
6
8
18
16
14
12
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
A1
A2
A3
A4
YA1
YA2
YA3
YA4
PIN ASSIGNMENT
OEA
1
20
V
CC
DATA
INPUTS
NONINVERTING
OUTPUTS
11
13
9
7
A1
YB4
A2
2
3
4
19
18
17
OEB
YA1
B4
B1
B2
YB1
YB2
YB3
A3
5
16
15
14
13
12
11
YA2
B3
15
17
5
3
B3
B4
YB3
YB4
6
YB2
A4
7
YA3
B2
8
YB1
GND
9
YA4
B1
10
1
OEA
OEB
OUTPUT
ENABLES
19
FUNCTION TABLE
INPUTS
OUTPUTS
YA, YB
OEA, OEB
A, B
L
L
H
L
H
X
L
H
Z
6/97
REV 1
1
Motorola, Inc. 1997