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MC74VHC240MEL PDF预览

MC74VHC240MEL

更新时间: 2024-11-04 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
6页 177K
描述
AHC/VHC SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, PLASTIC, SOIC-20

MC74VHC240MEL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:5.275 mm
Base Number Matches:1

MC74VHC240MEL 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC240 is an advanced high speed CMOS octal bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The MC74VHC240 is an inverting 3–state buffer, and has two active–low  
output enables. This device is designed to drive bus lines or buffer memory  
address registers.  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
High Speed: t  
= 3.6ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIH  
NIL CC  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.9V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 120 FETs or 30 Equivalent Gates  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
ORDERING INFORMATION  
MC74VHCXXXDW  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
LOGIC DIAGRAM  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
PIN ASSIGNMENT  
OEA  
1
20  
V
CC  
A1  
YB4  
A2  
2
3
4
19  
18  
17  
OEB  
YA1  
B4  
DATA  
INVERTING  
OUTPUTS  
INPUTS  
11  
13  
9
7
B1  
B2  
YB1  
YB2  
YB3  
A3  
5
16  
15  
14  
13  
12  
11  
YA2  
B3  
6
YB2  
A4  
7
YA3  
B2  
15  
17  
5
3
B3  
B4  
YB3  
YB4  
8
YB1  
GND  
9
YA4  
B1  
10  
1
OEA  
OEB  
OUTPUT  
ENABLES  
FUNCTION TABLE  
INPUTS  
19  
OUTPUTS  
YA, YB  
OEA, OEB  
A, B  
L
L
H
L
H
X
H
L
Z
6/97  
REV 0  
Motorola, Inc. 1997  

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