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MC74VHC240DWR2G PDF预览

MC74VHC240DWR2G

更新时间: 2024-11-24 12:22:51
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 133K
描述
Octal Bus Buffer/Line Driver Inverting with 3-State Outputs

MC74VHC240DWR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.01
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:3
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):12.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

MC74VHC240DWR2G 数据手册

 浏览型号MC74VHC240DWR2G的Datasheet PDF文件第2页浏览型号MC74VHC240DWR2G的Datasheet PDF文件第3页浏览型号MC74VHC240DWR2G的Datasheet PDF文件第4页浏览型号MC74VHC240DWR2G的Datasheet PDF文件第5页浏览型号MC74VHC240DWR2G的Datasheet PDF文件第6页浏览型号MC74VHC240DWR2G的Datasheet PDF文件第7页 
MC74VHC240  
Octal Bus Buffer/Line Driver  
Inverting with 3-State Outputs  
The MC74VHC240 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The MC74VHC240 is an inverting 3state buffer, and has two  
activelow output enables. This device is designed to drive bus lines  
or buffer memory address registers.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
20  
20  
VHC240  
AWLYYWWG  
1
SOIC20  
High Speed: t = 3.6 ns (Typ) at V = 5 V  
DW SUFFIX  
CASE 751D  
PD  
CC  
1
Low Power Dissipation: I = 4 μA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
20  
20  
VHC  
240  
Designed for 2 V to 5.5 V Operating Range  
1
ALYWG  
TSSOP20  
DT SUFFIX  
CASE 948E  
Low Noise: V  
= 0.9 V (Max)  
OLP  
G
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 120 FETs or 30 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
VHC240 = Specific Device Code  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
WW, W  
G or G  
= Work Week  
= PbFree Package  
(Note: Microdot may be in either location)  
OEA  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 OEB  
18 YA1  
17 B4  
16 YA2  
15 B3  
14 YA3  
13 B2  
12 YA4  
11 B1  
YB4  
A2  
ORDERING INFORMATION  
Device  
Package  
Shipping  
YB3  
A3  
MC74VHC240DWR2G SOIC20 1000 Units/Reel  
MC74VHC240DTR2G TSSOP20 2500 Units/Reel  
YB2  
A4  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
YB1  
GND 10  
FUNCTION TABLE  
Figure 1. Pin Assignment  
INPUTS  
OEA, OEB  
OUTPUTS  
YA, YB  
A, B  
L
L
H
L
H
X
H
L
Z
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 5  
MC74VHC240/D  

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