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MC74VHC1GT86DFT1

更新时间： 2024-11-04 05:30:07
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器栅极
页数 文件大小 规格书
6页 80K
描述
2−Input Exclusive OR Gate / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

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中文翻译

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MC74VHC1GT86DFT1 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOT-353包装说明：TSSOP, TSSOP5/6,.08
针数：5Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.62Is Samacsys：N
系列：AHC/VHCJESD-30 代码：R-PDSO-G5
JESD-609代码：e0长度：2 mm
逻辑集成电路类型：XOR GATE最大I（ol）：0.008 A
功能数量：1输入次数：2
端子数量：5最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：240
电源：3.3/5 VProp。Delay @ Nom-Sup：12 ns
传播延迟（tpd）：19.5 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：1.1 mm
子类别：Gates最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn80Pb20)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：1.25 mmBase Number Matches：1

MC74VHC1GT86DFT1 数据手册

 浏览型号MC74VHC1GT86DFT1的Datasheet PDF文件第2页浏览型号MC74VHC1GT86DFT1的Datasheet PDF文件第3页浏览型号MC74VHC1GT86DFT1的Datasheet PDF文件第4页浏览型号MC74VHC1GT86DFT1的Datasheet PDF文件第5页浏览型号MC74VHC1GT86DFT1的Datasheet PDF文件第6页 
MC74VHC1GT86  
2−Input Exclusive OR Gate /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT86 is an advanced high speed CMOS 2−input  
Exclusive OR gate fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT86 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT86 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
5
5
1
VM M G  
SC−88A/SOT−353/SC−70  
DF SUFFIX  
G
CASE 419A  
1
5
5
VM M G  
1
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
G
1
CASE 483  
V
CC  
= 0 V. These input and output structures help prevent device  
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
VM = Device Code  
M
G
= Date Code*  
= Pb−Free Package  
Features  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
• High Speed: t = 4.8 ns (Typ) at V = 5 V  
PD  
CC  
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
PIN ASSIGNMENT  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 83; Equivalent Gates = 16  
• Pb−Free Packages are Available  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
FUNCTION TABLE  
5
IN B  
IN A  
GND  
V
CC  
1
2
3
Inputs  
Output  
Y
A
B
L
L
L
H
L
L
H
H
L
OUT Y  
4
H
H
Figure 1. Pinout (Top View)  
H
IN A  
IN B  
= 1  
ORDERING INFORMATION  
OUT Y  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 15  
MC74VHC1GT86/D  
123456

中文翻译

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MC74VHC1GT86DFT1 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT1G86DCKT TI

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SN74AHCT1G86DCKR TI

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M74VHC1GT86DFT1G ONSEMI

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 2−Input Exclusive OR Gate / CMOS Logic Level Shifter with LSTTL−Compatible Inp

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