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MC74VHC1GT125DF2G PDF预览

MC74VHC1GT125DF2G

更新时间: 2024-11-04 13:02:59
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
页数 文件大小 规格书
8页 109K
描述
AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN

MC74VHC1GT125DF2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:SC-70, SC-88A, SOT-353, 5 PIN
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.31
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
长度:2 mm逻辑集成电路类型:BUS DRIVER
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mmBase Number Matches:1

MC74VHC1GT125DF2G 数据手册

 浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第2页浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第3页浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第4页浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第5页浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第6页浏览型号MC74VHC1GT125DF2G的Datasheet PDF文件第7页 
MC74VHC1GT125  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT125 is a single gate noninverting buffer fabricated  
with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS  
low power dissipation.  
The MC74VHC1GT125 requires the 3−state control input (OE) to be  
set High to place the output into the high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The device input is compatible with TTL−type input thresholds and the  
output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3.0 V  
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT125 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT125 to be used to interface 5 V circuits to 3 V  
SC−88A / SOT−353/SC−70  
DF SUFFIX  
W1d  
CASE 419A  
Pin 1  
d = Date Code  
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
W1d  
circuits. The output structures also provide protection when V = 0 V.  
CC  
CASE 483  
These input and output structures help prevent device destruction caused  
by supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
Pin 1  
d = Date Code  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
1
2
3
4
5
OE  
IN A  
GND  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 62; Equivalent Gates = 16  
OUT Y  
V
CC  
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
OE  
IN A  
GND  
V
CC  
5
4
1
2
L
H
X
L
L
L
H
Z
H
OUT Y  
3
Figure 1. Pinout (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
OE  
IN A  
OUT Y  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
December, 2003 − Rev. 8  
MC74VHC1GT125/D  

MC74VHC1GT125DF2G 替代型号

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