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MC74VHC1GT125DF1 PDF预览

MC74VHC1GT125DF1

更新时间: 2024-01-12 16:21:11
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
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8页 109K
描述
Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74VHC1GT125DF1 数据手册

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MC74VHC1GT125  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT125 is a single gate noninverting buffer fabricated  
with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS  
low power dissipation.  
The MC74VHC1GT125 requires the 3−state control input (OE) to be  
set High to place the output into the high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The device input is compatible with TTL−type input thresholds and the  
output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3.0 V  
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT125 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT125 to be used to interface 5 V circuits to 3 V  
SC−88A / SOT−353/SC−70  
DF SUFFIX  
W1d  
CASE 419A  
Pin 1  
d = Date Code  
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
W1d  
circuits. The output structures also provide protection when V = 0 V.  
CC  
CASE 483  
These input and output structures help prevent device destruction caused  
by supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
Pin 1  
d = Date Code  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
1
2
3
4
5
OE  
IN A  
GND  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 62; Equivalent Gates = 16  
OUT Y  
V
CC  
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
OE  
IN A  
GND  
V
CC  
5
4
1
2
L
H
X
L
L
L
H
Z
H
OUT Y  
3
Figure 1. Pinout (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
OE  
IN A  
OUT Y  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
December, 2003 − Rev. 8  
MC74VHC1GT125/D  

MC74VHC1GT125DF1 替代型号

型号 品牌 替代类型 描述 数据表
M74VHC1GT125DF2G ONSEMI

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Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs
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