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MC74VHC1GT08DFT2G PDF预览

MC74VHC1GT08DFT2G

更新时间: 2024-09-21 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 93K
描述
IC AHC/VHC SERIES, 2-INPUT AND GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN, Gate

MC74VHC1GT08DFT2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:SC-70, SC-88A, SOT-353, 5 PIN
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.03
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
长度:2 mm逻辑集成电路类型:AND GATE
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):16.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.25 mm
Base Number Matches:1

MC74VHC1GT08DFT2G 数据手册

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MC74VHC1GT08  
2-Input AND Gate/CMOS  
Logic Level Shifter  
The MC74VHC1GT08 is an advanced high speed CMOS 2–input AND  
gate fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
MARKING  
DIAGRAMS  
The device input is compatible with TTL–type input thresholds and the  
output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input, allowing  
the device to be used as a logic–level translator from 3.0 V CMOS logic to  
5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic  
while operating at the high–voltage power supply.  
SC–88A / SOT–353/SC–70  
DF SUFFIX  
d
VT  
CASE 419A  
The MC74VHC1GT08 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT08 to be used to interface 5 V circuits to 3 V  
Pin 1  
d = Date Code  
circuits. The output structures also provide protection when V  
= 0 V.  
CC  
These input and output structures help prevent device destruction caused  
by supply voltage – input/output voltage mismatch, battery backup, hot  
insertion, etc.  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
d
VT  
CASE 483  
High Speed: t  
= 3.5 ns (Typ) at V  
= 5 V  
PD  
Low Power Dissipation: I  
CC  
= 1 µA (Max) at T = 25°C  
Pin 1  
CC  
A
d = Date Code  
TTL–Compatible Inputs: V = 0.8 V; V = 2.0 V  
CMOS–Compatible Outputs: V  
IL  
IH  
> 0.8 V ; V  
< 0.1 V @Load  
OH  
CC OL CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 64; Equivalent Gates = 15  
PIN ASSIGNMENT  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
IN B  
IN A  
GND  
V
CC  
FUNCTION TABLE  
1
2
3
Inputs  
Output  
Y
A
B
L
L
L
H
L
L
L
H
H
L
4
OUT Y  
H
H
Figure 1. Pinout (Top View)  
ORDERING INFORMATION  
IN A  
IN B  
&
OUT Y  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
March, 2002 – Rev. 5  
MC74VHC1GT08/D  

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