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MC74VHC1GT04DTT3 PDF预览

MC74VHC1GT04DTT3

更新时间: 2024-11-04 05:30:07
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描述
Inverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs

MC74VHC1GT04DTT3 数据手册

 浏览型号MC74VHC1GT04DTT3的Datasheet PDF文件第2页浏览型号MC74VHC1GT04DTT3的Datasheet PDF文件第3页浏览型号MC74VHC1GT04DTT3的Datasheet PDF文件第4页 
Inverting Buffer / CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
MC74VHC1GT04  
The MC74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from  
3.0 V CMOS logic to 5.0V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT04 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT04 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when  
V
CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
• High Speed: t PD = 3.8 ns (Typ) at V CC = 5 V  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic  
Families  
• Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C  
• TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V  
• CMOS–Compatible Outputs: V OH > 0.8 V CC  
V OL < 0.1 V CC @Load  
;
• Chip Complexity: FETs = 105; Equivalent Gates = 26  
PIN ASSIGNMENT  
• Power Down Protection Provided on Inputs and Outputs  
MARKING DIAGRAMS  
5
4
1
2
3
VKd  
SC–70/SC–88A/SOT–353  
DF SUFFIX  
CASE 419A  
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VKd  
1
2
3
Figure 2. Logic Symbol  
SOT–23/TSOP–5/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
FUNCTION TABLE  
PIN ASSIGNMENT  
Inputs  
Output  
1
2
3
4
5
NC  
IN A  
A
L
Y
H
L
GND  
OUT Y  
V CC  
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VHT4–1/4  

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