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MC74VHC1GT04DFT2G PDF预览

MC74VHC1GT04DFT2G

更新时间: 2024-11-04 19:41:47
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
6页 119K
描述
AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5, SC-88A, SC-70, SOT-353, 5 PIN

MC74VHC1GT04DFT2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:TSSOP,
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.25
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
长度:2 mm逻辑集成电路类型:INVERTER
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):17.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.25 mm
Base Number Matches:1

MC74VHC1GT04DFT2G 数据手册

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MC74VHC1GT04  
Inverting Buffer /  
CMOS Logic Level Shifter  
LSTTLCompatible Inputs  
The MC74VHC1GT04 is a single gate inverting buffer fabricated  
with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS  
low power dissipation.  
http://onsemi.com  
MARKING  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTLtype input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logiclevel translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the highvoltage power supply.  
The MC74VHC1GT04 input structure provides protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT04 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection  
DIAGRAMS  
5
SC88A  
DF SUFFIX  
CASE 419A  
5
VK M G  
G
1
1
5
TSOP5  
DT SUFFIX  
CASE 483  
5
VK M G  
G
1
1
when V = 0 V. These input and output structures help prevent  
CC  
device destruction caused by supply voltage input/output voltage  
mismatch, battery backup, hot insertion, etc.  
VK = Device Code  
M
G
= Date Code*  
= PbFree Package  
Features  
High Speed: t = 3.8 ns (Typ) at V = 5 V  
PD  
CC  
(Note: Microdot may be in either location)  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
TTLCompatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
CMOSCompatible Outputs: V > 0.8 V ; V < 0.1 V @ Load  
OH  
CC OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 105; Equivalent Gates = 26  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
PIN ASSIGNMENT  
1
2
3
4
5
NC  
IN A  
GND  
OUT Y  
V
CC  
These Devices are PbFree and are RoHS Compliant  
FUNCTION TABLE  
A Input  
Y Output  
NC  
IN A  
GND  
1
2
3
5
V
CC  
L
H
L
H
4
OUT Y  
ORDERING INFORMATION  
Figure 1. Pinout (Top View)  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
1
IN A  
OUT Y  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
February, 2013 Rev. 16  
MC74VHC1GT04/D  

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