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MC74VHC1GT02DTT1 PDF预览

MC74VHC1GT02DTT1

更新时间: 2024-11-18 05:30:03
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 74K
描述
Single 2−Input NOR Gate/CMOS Logic Level Shifter LSTTL−Compatible Inputs

MC74VHC1GT02DTT1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:SC-59, SOT-23, TSOP-5
针数:5Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:7.37
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G5JESD-609代码:e0
长度:3 mm逻辑集成电路类型:NOR GATE
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:3.3/5 VProp。Delay @ Nom-Sup:9.5 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.5 mmBase Number Matches:1

MC74VHC1GT02DTT1 数据手册

 浏览型号MC74VHC1GT02DTT1的Datasheet PDF文件第2页浏览型号MC74VHC1GT02DTT1的Datasheet PDF文件第3页浏览型号MC74VHC1GT02DTT1的Datasheet PDF文件第4页浏览型号MC74VHC1GT02DTT1的Datasheet PDF文件第5页浏览型号MC74VHC1GT02DTT1的Datasheet PDF文件第6页 
MC74VHC1GT02  
Single 2−Input NOR Gate/  
CMOS Logic Level Shifter  
LSTTL−Compatible Inputs  
The MC74VHC1GT02 is a single gate 2−input NOR fabricated with  
silicon gate CMOS technology.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The internal circuit is composed of multiple stages, including a  
buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT02 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT02 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
5
5
1
VJ M G  
SC−88A/SC70−5/SOT−353  
DF SUFFIX  
G
1
CASE 419A  
5
5
VJ M G  
G
1
TSOP−5/SOT23−5/SC59−5  
DT SUFFIX  
1
V
CC  
= 0 V. These input and output structures help prevent device  
destruction caused by supply voltage − input/output voltage mismatch,  
battery backup, hot insertion, etc.  
CASE 483  
VJ = Device Code  
Features  
M
G
= Date Code*  
= Pb−Free Package  
High Speed: t = 4.7 ns (Typ) at V = 5 V  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
PD  
CC  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
CC  
A
IL  
IH  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 65  
Pb−Free Packages are Available  
PIN ASSIGNMENT  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
IN B  
1
2
3
V
CC  
FUNCTION TABLE  
Inputs  
Output  
Y
IN A  
A
B
L
L
L
H
L
H
L
L
L
GND  
4
OUT Y  
H
H
Figure 1. Pinout  
H
IN A  
IN B  
1  
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 11  
MC74VHC1GT02/D  

MC74VHC1GT02DTT1 替代型号

型号 品牌 替代类型 描述 数据表
M74VHC1GT02DTT1G ONSEMI

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Single 2−Input NOR Gate/CMOS Logic Level Shifter LSTTL−Compatible Inputs
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