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MC74VHC1GT02DFT2

更新时间： 2024-01-23 21:07:39
品牌 Logo 应用领域
乐山 - LRC 转换器电平转换器栅
页数 文件大小 规格书
4页 134K
描述
2-Input NOR Gate/CMOS Logic Level Shifter with LTTL-Compatible Inputs

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中文翻译

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MC74VHC1GT02DFT2 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOT-353包装说明：TSSOP,
针数：5Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.08
系列：AHC/VHCJESD-30 代码：R-PDSO-G5
长度：2 mm逻辑集成电路类型：NOR GATE
湿度敏感等级：1功能数量：1
输入次数：2端子数量：5
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：17.5 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.25 mmBase Number Matches：1

MC74VHC1GT02DFT2 数据手册

 浏览型号MC74VHC1GT02DFT2的Datasheet PDF文件第2页浏览型号MC74VHC1GT02DFT2的Datasheet PDF文件第3页浏览型号MC74VHC1GT02DFT2的Datasheet PDF文件第4页 
LESHAN RADIO COMPANY, LTD.  
2-Input NOR Gate / CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
MC74VHC1GT02  
The MC74VHC1GT02 is a single gate 2–input NOR fabricated with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from  
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power  
supply.  
The MC74VHC1GT02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT02 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when  
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
• High Speed: tPD = 4.7 ns (Typ) at VCC = 5 V  
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C  
• TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V  
• CMOS–Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.  
1 VCC @Load  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 65; Equivalent Gates = 14  
• Power Down Protection Provided on Inputs and Outputs  
MARKING DIAGRAMS  
5
4
1
2
3
VJd  
SC–88A / SOT–353/SC–70  
DF SUFFIX  
CASE 419A  
Y
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VJd  
1
2
3
Figure 2. Logic Symbol  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
FUNCTION TABLE  
PIN ASSIGNMENT  
Inputs  
Output  
1
2
3
4
5
IN B  
IN A  
A
L
B
L
Y
H
L
GND  
OUT Y  
V CC  
L
H
L
H
H
L
H
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VHT2–1/4  
1234

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