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MC74VHC1GT00DFT4 PDF预览

MC74VHC1GT00DFT4

更新时间: 2024-01-23 00:52:42
品牌 Logo 应用领域
乐山 - LRC 转换器电平转换器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 201K
描述
2-Input NAND Gate/CMOS Logic Level Shifter

MC74VHC1GT00DFT4 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:SC-70, SC-88A, SOT-353, 5 PIN
针数:5Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
JESD-609代码:e0长度:2 mm
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP5/6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:3.3/5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

MC74VHC1GT00DFT4 数据手册

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LESHAN RADIO COMPANY, LTD.  
2–Input NAND Gate / CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
MC74VHC1GT00  
The MC74VHC1GT00 is a single gate 2–input NAND fabricated with silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from  
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power  
supply.  
The MC74VHC1GT00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT00 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when  
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
Power Down Protection Provided on Inputs and Outputs  
High Speed: t PD = 3.1 ns (Typ) at V CC = 5 V  
Balanced Propagation Delays  
Low Power Dissipation: I CC = 2mA (Max) at T A = 2C  
Pin and Function Compatible with Other Standard Logic  
TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V  
Families  
CMOS–Compatible Outputs: V OH > 0.8 V CC ; V OL < 0.1  
Chip Complexity: FETs = 64; Equivalent Gates = 14  
V CC @Load  
MARKING DIAGRAMS  
5
4
1
2
VHd  
3
SC–70/SC–88A/SOT–353  
DF SUFFIX  
CASE 419A  
Pin 1  
Y
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VHd  
1
2
3
Figure 2. Logic Symbol  
SOT–23/TSOP–5/SC–59  
DT SUFFIX  
Pin 1  
CASE 483  
d = Date Code  
FUNCTION TABLE  
Inputs  
Output  
PIN ASSIGNMENT  
A
L
B
L
Y
H
H
H
L
1
2
3
4
5
IN B  
IN A  
L
H
L
GND  
OUT Y  
V CC  
H
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VHT0–1/4  

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