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MC74VHC1G14P5T5G PDF预览

MC74VHC1G14P5T5G

更新时间: 2024-10-02 11:01:47
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器栅极
页数 文件大小 规格书
6页 79K
描述
Single Inverter, Schmitt Trigger Input

MC74VHC1G14P5T5G 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SOT-953, 5 PINReach Compliance Code:compliant
Factory Lead Time:43 weeks 1 day风险等级:5.63
系列:AHC/VHCJESD-30 代码:R-PDSO-F5
长度:1 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSOF封装等效代码:FL5/6,.03,14
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TR峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:13.5 ns
传播延迟(tpd):20.5 ns施密特触发器:YES
座面最大高度:0.4 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.35 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.8 mm
Base Number Matches:1

MC74VHC1G14P5T5G 数据手册

 浏览型号MC74VHC1G14P5T5G的Datasheet PDF文件第2页浏览型号MC74VHC1G14P5T5G的Datasheet PDF文件第3页浏览型号MC74VHC1G14P5T5G的Datasheet PDF文件第4页浏览型号MC74VHC1G14P5T5G的Datasheet PDF文件第5页浏览型号MC74VHC1G14P5T5G的Datasheet PDF文件第6页 
MC74VHC1GT14  
Schmitt−Trigger Inverter /  
CMOS Logic Level Shifter  
LSTTL−Compatible Inputs  
The MC74VHC1GT14 is a single gate CMOS Schmitt−trigger  
inverter fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
http://onsemi.com  
MARKING  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT14 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT14 to be used to interface 5 V circuits to 3 V  
DIAGRAMS  
5
VC M G  
SC−88A/SC70−5/SOT−353  
DF SUFFIX  
G
CASE 419A  
1
5
5
VC M G  
circuits. The output structures also provide protection when V = 0 V.  
1
CC  
G
These input and output structures help prevent device destruction  
caused by supply voltage − input/output voltage mismatch, battery  
backup, hot insertion, etc. The MC74VHC1GT14 can be used to  
enhance noise immunity or to square up slowly changing waveforms.  
TSOP−5/SOT23−5/SC59−5  
DT SUFFIX  
1
CASE 483  
VC = Device Code  
M
G
= Date Code*  
= Pb−Free Package  
Features  
High Speed: t = 4.5 ns (Typ) at V = 5 V  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
PD  
CC  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
CC  
A
IL  
IH  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 100; Equivalent Gates = 25  
Pb−Free Packages are Available  
PIN ASSIGNMENT  
1
2
3
4
5
NC  
IN A  
GND  
OUT Y  
V
CC  
5
V
CC  
NC  
1
2
3
FUNCTION TABLE  
IN A  
A Input  
Y Output  
4
GND  
OUT Y  
L
H
L
H
Figure 1. Pinout (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
1
IN A  
OUT Y  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 12  
MC74VHC1GT14/D  

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