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MC74VCX16373 PDF预览

MC74VCX16373

更新时间： 2024-01-05 16:26:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
8页 145K
描述
LOW-VOLTAGE 1.8/2.5/3.3V 16-BIT TRANSPARENT LATCH

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MC74VCX16373 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP48,.3,20Reach Compliance Code：unknown
风险等级：5.92Is Samacsys：N
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
负载电容（CL）：30 pF逻辑集成电路类型：D LATCH
最大I（ol）：0.024 A位数：8
功能数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 VProp。Delay @ Nom-Sup：3 ns
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
Base Number Matches：1

MC74VCX16373 数据手册

 浏览型号MC74VCX16373的Datasheet PDF文件第2页浏览型号MC74VCX16373的Datasheet PDF文件第3页浏览型号MC74VCX16373的Datasheet PDF文件第4页浏览型号MC74VCX16373的Datasheet PDF文件第5页浏览型号MC74VCX16373的Datasheet PDF文件第6页浏览型号MC74VCX16373的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
VCX  
The MC74VCX16373 is an advanced performance, non–inverting  
16–bit transparent latch. It is designed for very high–speed, very  
low–power operation in 1.8V, 2.5V or 3.3V systems. The VCX16373 is  
byte controlled, with each byte functioning identically, but independently.  
Each byte has separate Output Enable and Latch Enable inputs. These  
control pins can be tied together for full 16–bit operation.  
LOW–VOLTAGE 1.8/2.5/3.3V  
16–BIT TRANSPARENT LATCH  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing to  
3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The MC74VCX16373 contains 16 D–type latches with 3–state  
3.6V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,  
data on the Dn inputs enters the latches. In this condition, the latches are  
transparent, (a latch output will change state each time its D input  
changes). When LE is LOW, the latch stores the information that was  
present on the D inputs a setup time preceding the HIGH–to–LOW  
transition of LE. The 3–state outputs are controlled by the Output Enable  
(OEn) inputs. When OE is LOW, the outputs are enabled. When OE is  
HIGH, the standard outputs are in the high impedance state, but this does  
not interfere with new data entering into the latches.  
DT SUFFIX  
48–LEAD PLASTIC TSSOP PACKAGE  
CASE 1201–01  
• Designed for Low Voltage Operation: V  
• 3.6V Tolerant Inputs and Outputs  
= 1.8–3.6V  
CC  
• High Speed Operation: 3.0ns max for 3.0 to 3.6V  
3.4ns max for 2.3 to 2.7V  
6.0ns max for 1.8V  
• Static Drive:  
±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
±6mA Drive at 1.8V  
PIN NAMES  
Pins  
Function  
• Supports Live Insertion and Withdrawal  
• I Specification Guarantees High Impedance When V  
• Near Zero Static Supply Current in All Three Logic States (20µA)  
OEn  
LEn  
D0–D15  
O0–O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
= 0V  
CC  
OFF  
Outputs  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds ±300mA  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
This document contains information on a product under development. Motorola reserves the right to  
change or discontinue this product without notice.  
10/97  
REV 0.1  
Motorola, Inc. 1997  
12345678

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