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MC74LVXT8053DTR2 PDF预览

MC74LVXT8053DTR2

更新时间： 2024-10-01 22:15:03
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
12页 246K
描述
Analog Multiplexer/Demultiplexer

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MC74LVXT8053DTR2 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.57
Is Samacsys：N模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXER
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm湿度敏感等级：1
信道数量：2功能数量：3
端子数量：16标称断态隔离度：37 dB
通态电阻匹配规范：25 Ω最大通态电阻 (Ron)：50 Ω
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2/6 V认证状态：Not Qualified
座面最大高度：1.2 mm最大信号电流：0.02 A
子类别：Multiplexer or Switches最大供电电流 (Isup)：0.16 mA
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
最长断开时间：30 ns最长接通时间：15 ns
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
Base Number Matches：1

MC74LVXT8053DTR2 数据手册

 浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第2页浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第3页浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第4页浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第5页浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第6页浏览型号MC74LVXT8053DTR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74LVXT8053 utilizes silicon–gate CMOS technology to  
achieve fast propagation delays, low ON resistances, and low OFF  
leakage currents. This analog multiplexer/demultiplexer controls  
analog voltages that may vary across the complete power supply range  
http://onsemi.com  
(from V  
to GND).  
CC  
The LVXT8053 is similar in pinout to the high–speed HC4053A,  
and the metal–gate MC14053B. The Channel–Select inputs determine  
which one of the Analog Inputs/Outputs is to be connected by means  
of an analog switch to the Common Output/Input. When the Enable  
pin is HIGH, all analog switches are turned off.  
The Channel–Select and Enable inputs are compatible with  
TTL–type input thresholds. The input protection circuitry on this  
device allows overvoltage tolerance on the input, allowing the device  
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V  
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while  
operating at the higher–voltage power supply.  
16–LEAD SOIC  
D SUFFIX  
CASE 751B  
16–LEAD TSSOP  
DT SUFFIX  
CASE 948F  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
V
Y
X
X1  
13  
X0  
12  
A
B
C
9
CC  
16  
15  
14  
11  
10  
The MC74LVXT8053 input structure provides protection when voltages  
up to 7V are applied, regardless of the supply voltage. This allows the  
MC74LVXT8053 to be used to interface 5V circuits to 3V circuits.  
1
2
3
4
5
6
7
8
This device has been designed so that the ON resistance (R ) is more  
on  
Y1  
Y0  
Z1  
Z
Z0 Enable NC GND  
linear over input voltage than R of metal–gate CMOS analog switches.  
on  
For detailed package marking information, see the Marking  
Diagram section on page 11 of this data sheet.  
• Fast Switching and Propagation Speeds  
• Low Crosstalk Between Switches  
• Diode Protection on All Inputs/Outputs  
FUNCTION TABLE – MC74LVXT8053  
• Analog Power Supply Range (V  
– GND) = 2.0 to 6.0 V  
CC  
Control Inputs  
• Digital (Control) Power Supply Range (V  
CC  
– GND) = 2.0 to 6.0 V  
Select  
• Improved Linearity and Lower ON Resistance Than Metal–Gate  
Enable  
C
B
A
ON Channels  
Counterparts  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0  
Y0  
Y0  
Y1  
Y1  
Y0  
Y0  
Y1  
Y1  
X0  
• Low Noise  
Z0  
Z0  
Z0  
Z1  
Z1  
Z1  
Z1  
X1  
X0  
X1  
X0  
X1  
X0  
X1  
• In Compliance With the Requirements of JEDEC Standard No. 7A  
L
LOGIC DIAGRAM  
H
H
H
H
X
Triple Single–Pole, Double–Position Plus Common Off  
L
H
H
X
12  
X0  
X1  
14  
X
Y
Z
13  
X SWITCH  
NONE  
2
1
X = Don’t Care  
Y0  
Y1  
15  
4
ANALOG  
INPUTS/OUTPUTS  
COMMON  
OUTPUTS/INPUTS  
Y SWITCH  
Z SWITCH  
ORDERING INFORMATION  
5
3
Z0  
Z1  
Device  
Package  
SOIC  
Shipping  
11  
10  
9
A
B
C
MC74LVXT8053D  
MC74LVXT8053DR2  
MC74LVXT8053DT  
48 Units/Rail  
2500 Units/Reel  
96 Units/Rail  
CHANNEL-SELECT  
INPUTS  
PIN 16 = V  
CC  
PIN 8 = GND  
SOIC  
6
ENABLE  
TSSOP  
NOTE: This device allows independent control of each switch.  
Channel–Select Input A controls the X–Switch, Input B controls  
the Y–Switch and Input C controls the Z–Switch  
MC74LVXT8053DTR2 TSSOP 2500 Units/Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74LVXT8053/D  
1234567...12

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