High–Performance Silicon–Gate CMOS
The MC74LVXT8053 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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(from V
to GND).
CC
The LVXT8053 is similar in pinout to the high–speed HC4053A,
and the metal–gate MC14053B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means
of an analog switch to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with
TTL–type input thresholds. The input protection circuitry on this
device allows overvoltage tolerance on the input, allowing the device
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while
operating at the higher–voltage power supply.
16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
V
Y
X
X1
13
X0
12
A
B
C
9
CC
16
15
14
11
10
The MC74LVXT8053 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT8053 to be used to interface 5V circuits to 3V circuits.
1
2
3
4
5
6
7
8
This device has been designed so that the ON resistance (R ) is more
on
Y1
Y0
Z1
Z
Z0 Enable NC GND
linear over input voltage than R of metal–gate CMOS analog switches.
on
For detailed package marking information, see the Marking
Diagram section on page 11 of this data sheet.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
FUNCTION TABLE – MC74LVXT8053
• Analog Power Supply Range (V
– GND) = 2.0 to 6.0 V
CC
Control Inputs
• Digital (Control) Power Supply Range (V
CC
– GND) = 2.0 to 6.0 V
Select
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Enable
C
B
A
ON Channels
Counterparts
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
• Low Noise
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
• In Compliance With the Requirements of JEDEC Standard No. 7A
L
LOGIC DIAGRAM
H
H
H
H
X
Triple Single–Pole, Double–Position Plus Common Off
L
H
H
X
12
X0
X1
14
X
Y
Z
13
X SWITCH
NONE
2
1
X = Don’t Care
Y0
Y1
15
4
ANALOG
INPUTS/OUTPUTS
COMMON
OUTPUTS/INPUTS
Y SWITCH
Z SWITCH
ORDERING INFORMATION
5
3
Z0
Z1
Device
Package
SOIC
Shipping
11
10
9
A
B
C
MC74LVXT8053D
MC74LVXT8053DR2
MC74LVXT8053DT
48 Units/Rail
2500 Units/Reel
96 Units/Rail
CHANNEL-SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
SOIC
6
ENABLE
TSSOP
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
MC74LVXT8053DTR2 TSSOP 2500 Units/Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
March, 2000 – Rev. 2
MC74LVXT8053/D