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MC74LVXC3245DWR2G PDF预览

MC74LVXC3245DWR2G

更新时间: 2024-02-16 23:42:44
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 88K
描述
Configurable Dual Supply Octal Transceiver

MC74LVXC3245DWR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
其他特性:3.3V SUPPLY FOR PORT A; 5V SUPPLY FOR PORT B控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:15.395 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3/5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40翻译:3V & 3/5V
宽度:7.5 mmBase Number Matches:1

MC74LVXC3245DWR2G 数据手册

 浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第2页浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第3页浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第4页浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第5页浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第6页浏览型号MC74LVXC3245DWR2G的Datasheet PDF文件第7页 
MC74LVXC3245  
Configurable Dual Supply  
Octal Transceiver  
with 3−State Outputs for 3 V Systems  
The 74LVXC3245 is a 24−pin dual−supply, octal configurable  
voltage interface transceiver especially well suited for PCMCIA and  
http://onsemi.com  
MARKING  
other real time configurable I/O applications. The V  
pin accepts a  
CCA  
3.0 V supply level; the A port is a dedicated 3.0 V port. The V  
pin  
CCB  
DIAGRAMS  
accepts a 3.0 V−to−5.0 V supply level. The B port is configured to  
track the V supply level. A 5.0 V level on the V pin will  
CCB  
CCB  
24  
configure the I/O pins at a 5.0 V level and a 3.0 V V  
will configure  
CCB  
24  
the I/O pins at a 3.0 V level. The A port interfaces with a 3.0 V host  
system and the B port to the card slots. This device will allow the  
LVX  
3245  
AWLYYWW  
SOIC−24  
DW SUFFIX  
CASE 751E  
V
CCB  
voltage source pin and I/O pins on the B port to float when OE is  
1
High. This feature is necessary to buffer data to and from a PCMCIA  
socket that permits PCMCIA cards to be inserted and removed during  
normal operation. The Transmit/Receive (T/R) input determines the  
direction of data flow. Transmit (active−High) enables data from the A  
port to B port. Receive (active−Low) enables data from the B port to  
the A port.  
1
24  
24  
TSSOP−24  
DT SUFFIX  
CASE 948H  
LVXC3245  
AWLYYWW  
1
Features  
1
Bidirectional Interface Between 3.0 V and 3.0 V/5.0 V Buses  
Control Inputs Compatible with TTL Level  
Outputs Source/Sink Up to 24 mA  
Guaranteed Simultaneous Switching Noise Level and Dynamic  
Threshold Performance  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
= Work Week  
Available in SOIC and TSSOP Packages  
Flexible V  
Operating Range  
CCB  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Allows B Port and V  
Functionally Compatible With the 74 Series 245  
Pb−Free Packages are Available*  
to Float Simultaneously When OE is High  
CCB  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
March, 2005 − Rev. 4  
MC74LVXC3245/D  

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