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MC74LVX573DTR2

更新时间: 2024-02-18 22:31:11
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器
页数 文件大小 规格书
8页 102K
描述
Octal D-Type Latch with 3-State Outputs With 5 V−Tolerant Inputs

MC74LVX573DTR2 技术参数

生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.12JESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端子数量:20封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:1.2 mm表面贴装:YES
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

MC74LVX573DTR2 数据手册

 浏览型号MC74LVX573DTR2的Datasheet PDF文件第2页浏览型号MC74LVX573DTR2的Datasheet PDF文件第3页浏览型号MC74LVX573DTR2的Datasheet PDF文件第4页浏览型号MC74LVX573DTR2的Datasheet PDF文件第5页浏览型号MC74LVX573DTR2的Datasheet PDF文件第6页浏览型号MC74LVX573DTR2的Datasheet PDF文件第7页 
MC74LVX573  
Octal D−Type Latch  
with 3−State Outputs  
With 5 V−Tolerant Inputs  
The MC74LVX573 is an advanced high speed CMOS octal latch  
with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing  
the interface of 5.0 V systems to 3.0 V systems.  
This 8−bit D−type latch is controlled by a latch enable input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
Features  
LVX573  
AWLYYWW  
High Speed: t = 6.4 ns (Typ) at V = 3.3 V  
PD  
CC  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
SOIC−20  
DW SUFFIX  
CASE 751D  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
1
Low Noise: V  
= 0.8 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: Human Body Model > 2000 V;  
Machine Model > 200 V  
LVX  
573  
ALYW  
Pb−Free Packages are Available*  
TSSOP−20  
DT SUFFIX  
CASE 948E  
V
O0  
19  
O1  
18  
O2  
17  
O3  
16  
O4  
15  
O5  
14  
O6  
13  
O7  
12  
LE  
11  
CC  
LVX573  
AWLYWW  
20  
SOEIAJ−20  
M SUFFIX  
CASE 967  
A
= Assembly Location  
= Year  
1
2
3
4
5
6
7
9
8
10  
WL, L = Wafer Lot  
Y, YY  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7 GND  
W, WW = Work Week  
Figure 1. 20−Lead Pinout (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
March, 2005 − Rev. 3  
MC74LVX573/D  

MC74LVX573DTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74LVX573DTR2G ONSEMI

完全替代

Octal D-Type Latch with 3-State Outputs
MC74LVX573DTG ONSEMI

完全替代

Octal D-Type Latch with 3-State Outputs
MC74LVX573DT ONSEMI

完全替代

LOW-VOLTAGE CMOS

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