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MC74LVX374M PDF预览

MC74LVX374M

更新时间: 2024-11-13 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
7页 171K
描述
LOW-VOLTAGE CMOS

MC74LVX374M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.6
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:55000000 Hz最大I(ol):0.004 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:16 ns
传播延迟(tpd):23 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.275 mm

MC74LVX374M 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LVX374 is an advanced high speed CMOS octal D–type  
flip–flop with 3–state outputs. The inputs tolerate voltages up to 7V,  
allowing the interface of 5V systems to 3V systems.  
This 8–bit D–type flip–flop is controlled by a clock input and an output  
enable input. When the output enable input is high, the eight outputs are  
in a high impedance state.  
LOW–VOLTAGE CMOS  
High Speed: f  
= 160MHz (Typ) at V  
= 3.3V  
max  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
V
O7  
19  
D7  
18  
D6  
17  
O6  
16  
O5  
15  
D5  
14  
D4  
13  
O4  
12  
CP  
11  
CC  
20  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
1
2
3
4
5
6
7
9
8
10  
OE  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
GND  
PIN NAMES  
Figure 1. 20–Lead Pinout (Top View)  
Pins  
Function  
OE  
CP  
D0–D7  
O0–O7  
Output Enable Input  
Clock Pulse Input  
Data Inputs  
3–State Outputs  
6/97  
Motorola, Inc. 1997  
REV 0  

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