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MC74LVX373MEL PDF预览

MC74LVX373MEL

更新时间: 2024-11-14 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 102K
描述
Octal D-Type Latch with 3-State Outputs With 5V−Tolerant Inputs

MC74LVX373MEL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.66
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:3
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:14.5 ns传播延迟(tpd):22 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.275 mmBase Number Matches:1

MC74LVX373MEL 数据手册

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MC74LVX373  
Octal D−Type Latch  
with 3−State Outputs  
With 5V−Tolerant Inputs  
The MC74LVX373 is an advanced high speed CMOS octal latch  
with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing  
the interface of 5.0 V systems to 3.0 V systems.  
This 8−bit D−type latch is controlled by a latch enable input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
Features  
SOIC−20  
DW SUFFIX  
CASE 751D  
LVX373  
AWLYYWW  
20  
High Speed: t = 5.8 ns (Typ) at V = 3.3 V  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
Power Down Protection Provided on Inputs  
PD  
CC  
1
CC  
A
1
Balanced Propagation Delays  
20  
1
Low Noise: V  
= 0.8 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance:  
LVX  
373  
ALYW  
TSSOP−20  
DT SUFFIX  
CASE 948E  
20  
1
Human Body Model > 2000 V;  
Machine Model > 200 V  
Pb−Free Packages are Available*  
20  
SOEIAJ−20  
M SUFFIX  
CASE 967  
74LVX373  
AWLYWW  
20  
1
1
V
O7  
19  
D7  
18  
D6  
17  
O6  
16  
O5  
15  
D5  
14  
D4  
13  
O4  
12  
LE  
11  
CC  
20  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
W, WW = Work Week  
PIN NAMES  
1
2
3
4
5
6
7
9
8
10  
Pins  
Function  
OE  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3 GND  
OE  
LE  
D0−D7  
O0−O7  
Output Enable Input  
Latch Enable Input  
Data Inputs  
Figure 1. 20−Lead Pinout (Top View)  
3−State Latch Outputs  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
March, 2005 − Rev. 2  
MC74LVX373/D  

MC74LVX373MEL 替代型号

型号 品牌 替代类型 描述 数据表
MC74LVX373MG ONSEMI

完全替代

Octal D-Type Latch with 3-State Outputs With 5V−Tolerant Inputs
MC74LVX373MELG ONSEMI

完全替代

Octal D-Type Latch with 3-State Outputs With 5V−Tolerant Inputs
MC74LVX373M ONSEMI

完全替代

LOW-VOLTAGE CMOS

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