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MC74LVX373DT PDF预览

MC74LVX373DT

更新时间: 2024-11-13 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 172K
描述
LOW-VOLTAGE CMOS

MC74LVX373DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.1Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
电源:3.3 VProp。Delay @ Nom-Sup:14.5 ns
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

MC74LVX373DT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LVX373 is an advanced high speed CMOS octal latch with  
3–state outputs. The inputs tolerate voltages up to 7V, allowing the  
interface of 5V systems to 3V systems.  
This 8–bit D–type latch is controlled by a latch enable input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
LOW–VOLTAGE CMOS  
High Speed: t  
= 5.8ns (Typ) at V  
= 3.3V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
V
O7  
19  
D7  
18  
D6  
17  
O6  
16  
O5  
15  
D5  
14  
D4  
13  
O4  
12  
LE  
11  
CC  
20  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
1
2
3
4
5
6
7
9
8
10  
OE  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
GND  
PIN NAMES  
Figure 1. 20–Lead Pinout (Top View)  
Pins  
Function  
OE  
LE  
D0–D7  
O0–O7  
Output Enable Input  
Latch Enable Input  
Data Inputs  
3–State Latch Outputs  
6/97  
Motorola, Inc. 1997  
REV 0  

MC74LVX373DT 替代型号

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