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MC74LVQ373 PDF预览

MC74LVQ373

更新时间: 2024-11-24 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
8页 217K
描述
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MC74LVQ373 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LVQ373 is a high performance, non–inverting octal  
transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ373  
is suitable for TTL level bus oriented applications where a memory  
element is required.  
LVQ  
The MC74LVQ373 contains 8 D–type latches with 3–state outputs.  
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters  
the latches. In this condition, the latches are transparent, i.e., a latch  
output will change state each time its D input changes. When LE is LOW,  
the latches store the information that was present on the D inputs a setup  
time preceding the HIGH–to–LOW transition of LE. The 3–state standard  
outputs are controlled by the Output Enable (OE) input. When OE is  
LOW, the standard outputs are enabled. When OE is HIGH, the standard  
outputs are in the high impedance state, but this does not interfere with  
new data entering into the latches. Current drive capability is 12mA at the  
outputs.  
LOW–VOLTAGE  
CMOS OCTAL  
TRANSPARENT LATCH  
DW SUFFIX  
PLASTIC SOIC  
CASE 751D–04  
20  
1
Designed for 2.7 to 3.6V V  
Noise Applications  
Operation – Ideal for Low Power/Low  
CC  
Guaranteed Simultaneous Switching Noise Level and Dynamic  
Threshold Performance  
M SUFFIX  
PLASTIC SOIC EIAJ  
20  
Guaranteed Skew Specifications  
CASE 967–01  
1
Guaranteed Incident Wave Switching into 75  
LowStaticSupplyCurrent(10µA)SubstantiallyReducesSystemPower  
Requirements  
SD SUFFIX  
PLASTIC SSOP  
CASE 940C–03  
Latchup Performance Exceeds 500mA  
20  
ESD Performance: Human Body Model >2000V  
1
DT SUFFIX  
PLASTIC TSSOP  
CASE 948E–02  
20  
Pinout: 20–Lead (Top View)  
1
V
O7  
19  
D7  
18  
D6  
17  
O6  
16  
O5  
15  
D5  
14  
D4  
13  
O4  
12  
LE  
11  
CC  
20  
PIN NAMES  
Pins  
Function  
OE  
Output Enable Input  
LE  
D0–D7  
O0–O7  
Latch Enable Input  
Data Inputs  
3–State Latch Outputs  
1
2
3
4
5
6
7
9
8
10  
OE  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
GND  
12/95  
Motorola, Inc. 1995  
REV 1  

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