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MC74LVQ02M PDF预览

MC74LVQ02M

更新时间: 2024-11-20 22:26:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
7页 189K
描述
LOW-VOLTAGE CMOS QUAD 2-INPUT NOR GATE

MC74LVQ02M 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:N系列:LVQ
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.012 A
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

MC74LVQ02M 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LVQ02 is a high performance, quad 2–input NOR gate  
operating from a 2.7 to 3.6V supply. High impedance TTL compatible  
inputs significantly reduce current loading to input drivers while TTL  
compatible outputs offer improved switching noise performance.  
LVQ  
Current drive capability is 12mA at the outputs.  
LOW–VOLTAGE CMOS  
QUAD 2–INPUT NOR GATE  
Designed for 2.7 to 3.6V V  
Noise Applications  
Operation – Ideal for Low Power/Low  
CC  
Guaranteed Simultaneous Switching Noise Level and Dynamic  
Threshold Performance  
Guaranteed Skew Specifications  
D SUFFIX  
PLASTIC SOIC  
CASE 751A–03  
Guaranteed Incident Wave Switching into 75  
14  
LowStaticSupplyCurrent(10µA)SubstantiallyReducesSystemPower  
Requirements  
1
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V  
M SUFFIX  
14  
PLASTIC SOIC EIAJ  
CASE 965–01  
1
Pinout: 14–Lead (Top View)  
V
O2  
13  
B2  
12  
A2  
11  
O3  
10  
B3  
9
A3  
8
CC  
14  
SD SUFFIX  
PLASTIC SSOP  
14  
CASE 940A–03  
1
DT SUFFIX  
PLASTIC TSSOP  
14  
1
2
3
4
5
6
7
CASE 948G–01  
1
O0  
A0  
B0  
O1  
A1  
B1  
GND  
LOGIC DIAGRAM  
PIN NAMES  
2
A0  
Pins  
Function  
1
O0  
O1  
O2  
O3  
3
5
B0  
A1  
An, Bn  
On  
Data Inputs  
Outputs  
4
13  
10  
6
B1  
A2  
11  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
On  
12  
8
B2  
A3  
An  
Bn  
L
L
H
H
L
H
L
H
L
L
L
9
B3  
H
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/95  
REV 0  
Motorola, Inc. 1995  

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