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MC74LCX74MR2 PDF预览

MC74LCX74MR2

更新时间: 2024-11-21 21:12:03
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 148K
描述
LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SO-14

MC74LCX74MR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.08
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:10.2 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
传播延迟(tpd):8.4 ns认证状态:Not Qualified
座面最大高度:2.05 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:5.275 mm
最小 fmax:150 MHzBase Number Matches:1

MC74LCX74MR2 数据手册

 浏览型号MC74LCX74MR2的Datasheet PDF文件第2页浏览型号MC74LCX74MR2的Datasheet PDF文件第3页浏览型号MC74LCX74MR2的Datasheet PDF文件第4页浏览型号MC74LCX74MR2的Datasheet PDF文件第5页浏览型号MC74LCX74MR2的Datasheet PDF文件第6页浏览型号MC74LCX74MR2的Datasheet PDF文件第7页 
MC74LCX74  
Low-Voltage CMOS Dual  
D-Type Flip-Flop  
With 5 VTolerant Inputs  
The MC74LCX74 is a high performance, dual Dtype flipflop  
with asynchronous clear and set inputs and complementary (O, O)  
outputs. It operates from a 2.3 to 3.6 V supply. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
performance. A V specification of 5.5 V allows MC74LCX74 inputs  
I
SOIC14  
D SUFFIX  
CASE 751A  
LCX74G  
AWLYWW  
to be safely driven from 5.0 V devices.  
14  
14  
The MC74LCX74 consists of 2 edgetriggered flipflops with  
individual Dtype inputs. The flipflop will store the state of  
individual D inputs, that meet the setup and hold time requirements, on  
the LOWtoHIGH Clock (CP) transition.  
1
1
14  
Features  
TSSOP14  
DT SUFFIX  
CASE 948G  
LCX  
74  
Designed for 2.3 V to 3.6 V V Operation  
CC  
ALYWG  
1
G
5.0 V Tolerant Inputs Interface Capability With 5.0 V TTL Logic  
1
LVTTL Compatible  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
W, WW = Work Week  
Near Zero Static Supply Current in All Three Logic States (10 mA)  
G or G  
= PbFree Package  
Substantially Reduces System Power Requirements  
(Note: Microdot may be in either location)  
Latchup Performance Exceeds 500 mA  
ESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
October, 2012 Rev. 8  
MC74LCX74/D  

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