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MC74LCX646DW PDF预览

MC74LCX646DW

更新时间: 2024-11-05 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器
页数 文件大小 规格书
10页 172K
描述
LOW-VOLTAGE CMOS OCTAL TRANSCEIVER/ REGISTERED TRANSCEIVER

MC74LCX646DW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOIC-24
针数:24Reach Compliance Code:not_compliant
风险等级:5.19Is Samacsys:N
其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:15.4 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

MC74LCX646DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX646 is a high performance, non–inverting octal  
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.  
High impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
LOW–VOLTAGE CMOS  
OCTAL TRANSCEIVER/  
REGISTERED TRANSCEIVER  
switching noise performance. A V specification of 5.5V allows  
I
MC74LCX646 inputs to be safely driven from 5V devices. The  
MC74LCX646 is suitable for memory address driving and all TTL level  
bus oriented transceiver applications.  
Data on the A or B bus will be clocked into the registers as the  
appropriate clock pin goes from a LOW–to–HIGH logic level. Output  
Enable (OE) and DIR pins are provided to control the transceiver outputs.  
In the transceiver mode, data present at the high impedance port may be  
stored in either the A or the B register or in both. The select controls (SBA,  
SAB) can multiplex stored and real–time (transparent mode) data. The  
direction control (DIR) determines which bus will receive data when the  
enable OE is active LOW. In the isolation mode (OE HIGH), A data may  
be stored in the B register or B data may be stored in the A register. Only  
one of the two buses, A or B, may be driven at one time.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751E–04  
24  
1
SD SUFFIX  
PLASTIC SSOP  
24  
Designed for 2.7 to 3.6V V  
CC  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
Operation  
CASE 940D–03  
1
I  
OFF  
LVTTL Compatible  
Specification Guarantees High Impedance When V  
= 0V  
CC  
DT SUFFIX  
PLASTIC TSSOP  
24  
CASE 948H–01  
LVCMOS Compatible  
1
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
PIN NAMES  
Pins  
Function  
V
CBA SBA OE  
B0  
20  
B1  
19  
B2  
18  
B3  
17  
B4  
16  
B5  
15  
B6  
14  
B7  
13  
CC  
A0–A7  
B0–B7  
CAB, CBA  
SAB, SBA  
DIR, OE  
Side A Inputs/Outputs  
Side B Inputs/Outputs  
Clock Pulse Inputs  
Select Control Inputs  
Output Enable Inputs  
24  
23  
22  
21  
Pinout: 24–Lead Package (Top View)  
1
2
3
4
5
6
7
9
11  
8
10  
A6  
12  
CAB SAB DIR  
A0  
A1  
A2  
A3  
A4  
A5  
A7 GND  
11/96  
Motorola, Inc. 1996  
REV 2  

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