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MC74LCX574DWR2G PDF预览

MC74LCX574DWR2G

更新时间: 2024-09-15 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 92K
描述
Low-Voltage CMOS Octal D-Type Flip-Flop Flow Through Pinout With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

MC74LCX574DWR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.43
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.024 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

MC74LCX574DWR2G 数据手册

 浏览型号MC74LCX574DWR2G的Datasheet PDF文件第2页浏览型号MC74LCX574DWR2G的Datasheet PDF文件第3页浏览型号MC74LCX574DWR2G的Datasheet PDF文件第4页浏览型号MC74LCX574DWR2G的Datasheet PDF文件第5页浏览型号MC74LCX574DWR2G的Datasheet PDF文件第6页浏览型号MC74LCX574DWR2G的Datasheet PDF文件第7页 
MC74LCX574  
Low−Voltage CMOS  
Octal D−Type Flip−Flop  
Flow Through Pinout  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
MARKING  
The MC74LCX574 is a high performance, non−inverting octal  
D−type flip−flop operating from a 2.3 to 3.6 V supply. High  
impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
DIAGRAMS  
20  
SOIC−20  
DW SUFFIX  
CASE 751D  
switching noise performance. A V specification of 5.5 V allows  
I
LCX574  
AWLYYWW  
20  
MC74LCX574 inputs to be safely driven from 5.0 V devices.  
The MC74LCX574 consists of 8 edge−triggered flip−flops with  
individual D−type inputs and 3−state true outputs. The buffered clock  
and buffered Output Enable (OE) are common to all flip−flops. The  
eight flip−flops will store the state of individual D inputs that meet the  
setup and hold time requirements on the LOW−to−HIGH Clock (CP)  
transition. With the OE LOW, the contents of the eight flip−flops are  
available at the outputs. When the OE is HIGH, the outputs go to the  
high impedance state. The OE input level does not affect the operation  
of the flip−flops. The LCX574 flow through design facilitates easy PC  
board layout.  
1
1
20  
LCX  
574  
ALYW  
TSSOP−20  
DT SUFFIX  
CASE 948E  
20  
1
1
Features  
20  
Designed for 2.3 to 3.6 V V Operation  
5 V Tolerant − Interface Capability With 5 V TTL Logic  
Supports Live Insertion and Withdrawal  
CC  
SOEIAJ−20  
M SUFFIX  
CASE 967  
1
74LCX574  
AWLYWW  
20  
1
I  
Specification Guarantees High Impedance When V = 0 V  
OFF  
CC  
LVTTL Compatible  
LVCMOS Compatible  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500 mA  
W, WW = Work Week  
ESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
Pb−Free Packages are Available*  
dimensions section on page 3 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 − Rev. 5  
MC74LCX574/D  

MC74LCX574DWR2G 替代型号

型号 品牌 替代类型 描述 数据表
74LCX574WM FAIRCHILD

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