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MC74LCX573SDR2

更新时间： 2024-09-15 20:07:51
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件
页数 文件大小 规格书
9页 132K
描述
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20

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中文翻译

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MC74LCX573SDR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP,
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.1
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G20
JESD-609代码：e0长度：7.2 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：225
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
座面最大高度：2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

MC74LCX573SDR2 数据手册

 浏览型号MC74LCX573SDR2的Datasheet PDF文件第2页浏览型号MC74LCX573SDR2的Datasheet PDF文件第3页浏览型号MC74LCX573SDR2的Datasheet PDF文件第4页浏览型号MC74LCX573SDR2的Datasheet PDF文件第5页浏览型号MC74LCX573SDR2的Datasheet PDF文件第6页浏览型号MC74LCX573SDR2的Datasheet PDF文件第7页 
MC74LCX573  
Low-Voltage CMOS  
Octal Transparent Latch  
Flow Through Pinout  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
MARKING  
The MC74LCX573 is a high performance, non−inverting octal  
transparent latch operating from a 2.3 to 3.6 V supply. High  
impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
DIAGRAMS  
20  
LCX573  
AWLYYWWG  
switching noise performance. A V specification of 5.5 V allows  
I
MC74LCX573 inputs to be safely driven from 5.0 V devices.  
The MC74LCX573 contains 8 D−type latches with 3−state standard  
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn  
inputs enters the latches. In this condition, the latches are transparent,  
i.e., a latch output will change state each time its D input changes.  
When LE is LOW, the latches store the information that was present  
on the D inputs a setup time preceding the HIGH−to−LOW transition  
of LE. The 3−state standard outputs are controlled by the Output  
Enable (OE) input. When OE is LOW, the standard outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The LCX573 flow through design facilitates easy PC  
board layout.  
SOIC−20 WB  
DW SUFFIX  
CASE 751D  
1
LCX  
573  
ALYWG  
TSSOP−20  
DT SUFFIX  
CASE 948E  
G
A
L, WL  
Y, YY  
=
=
=
Assembly Location  
Wafer Lot  
Year  
Features  
W, WW = Work Week  
G or G  
= Pb−Free Package  
• Designed for 2.3 to 3.6 V V Operation  
• 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
• Supports Live Insertion and Withdrawal  
CC  
(Note: Microdot may be in either location)  
• I  
Specification Guarantees High Impedance When V = 0 V  
OFF  
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
• LVTTL Compatible  
• LVCMOS Compatible  
• 24 mA Balanced Output Sink and Source Capability  
• Near Zero Static Supply Current in All Three Logic States (10 mA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds 500 mA  
• ESD Performance:  
♦ Human Body Model >2000 V  
♦ Machine Model >200 V  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
January, 2013 − Rev. 12  
MC74LCX573/D  
1234567...9

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