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MC74LCX573DTR2

更新时间: 2024-11-21 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 94K
描述
Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

MC74LCX573DTR2 数据手册

 浏览型号MC74LCX573DTR2的Datasheet PDF文件第2页浏览型号MC74LCX573DTR2的Datasheet PDF文件第3页浏览型号MC74LCX573DTR2的Datasheet PDF文件第4页浏览型号MC74LCX573DTR2的Datasheet PDF文件第5页浏览型号MC74LCX573DTR2的Datasheet PDF文件第6页浏览型号MC74LCX573DTR2的Datasheet PDF文件第7页 
MC74LCX573  
Low−Voltage CMOS  
Octal Transparent Latch  
Flow Through Pinout  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
MARKING  
The MC74LCX573 is a high performance, non−inverting octal  
transparent latch operating from a 2.3 to 3.6 V supply. High  
impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
DIAGRAMS  
20  
SOIC−20  
DW SUFFIX  
CASE 751D  
switching noise performance. A V specification of 5.5 V allows  
I
LCX573  
AWLYYWWG  
20  
MC74LCX573 inputs to be safely driven from 5.0 V devices.  
The MC74LCX573 contains 8 D−type latches with 3−state standard  
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn  
inputs enters the latches. In this condition, the latches are transparent,  
i.e., a latch output will change state each time its D input changes.  
When LE is LOW, the latches store the information that was present  
on the D inputs a setup time preceding the HIGH−to−LOW transition  
of LE. The 3−state standard outputs are controlled by the Output  
Enable (OE) input. When OE is LOW, the standard outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The LCX573 flow through design facilitates easy PC  
board layout.  
1
1
20  
LCX  
573  
TSSOP−20  
DT SUFFIX  
20  
ALYWG  
CASE 948E  
1
G
1
20  
SOEIAJ−20  
M SUFFIX  
CASE 967  
1
Features  
74LCX573  
AWLYWWG  
Designed for 2.3 to 3.6 V V Operation  
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
CC  
20  
1
Supports Live Insertion and Withdrawal  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
LVTTL Compatible  
W, WW = Work Week  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
G
G
= Pb−Free Package  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Near Zero Static Supply Current in All Three Logic States (10 mA)  
Substantially Reduces System Power Requirements  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
Latchup Performance Exceeds 500 mA  
ESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
May, 2005 − Rev. 7  
MC74LCX573/D  

MC74LCX573DTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74LCX573DTG ONSEMI

完全替代

Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Input
MC74LCX573DT ONSEMI

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