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MC74LCX573 PDF预览

MC74LCX573

更新时间: 2024-09-12 22:12:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
8页 162K
描述
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MC74LCX573 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX573 is a high performance, non–inverting octal  
transparent latch operating from a 2.7 to 3.6V supply. High impedance  
TTL compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE  
CMOS OCTAL  
TRANSPARENT LATCH  
performance. A V specification of 5.5V allows MC74LCX573 inputs to be  
I
safely driven from 5V devices.  
The MC74LCX573 contains 8 D–type latches with 3–state standard  
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs  
enters the latches. In this condition, the latches are transparent, i.e., a  
latch output will change state each time its D input changes. When LE is  
LOW, the latches store the information that was present on the D inputs a  
setup time preceding the HIGH–to–LOW transition of LE. The 3–state  
standard outputs are controlled by the Output Enable (OE) input. When  
OE is LOW, the standard outputs are enabled. When OE is HIGH, the  
standard outputs are in the high impedance state, but this does not  
interfere with new data entering into the latches. The LCX573 flow  
through design facilitates easy PC board layout.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751D–04  
20  
1
M SUFFIX  
PLASTIC SOIC EIAJ  
20  
Designed for 2.7 to 3.6V V  
CC  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
Operation  
CASE 967–01  
1
I  
OFF  
LVTTL Compatible  
Specification Guarantees High Impedance When V  
= 0V  
CC  
SD SUFFIX  
PLASTIC SSOP  
CASE 940C–03  
20  
LVCMOS Compatible  
1
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948E–02  
Latchup Performance Exceeds 500mA  
20  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
1
Pinout: 20–Lead (Top View)  
V
O0  
19  
O1  
18  
O2  
17  
O3  
16  
O4  
15  
O5  
14  
O6  
13  
O7  
12  
LE  
11  
PIN NAMES  
CC  
20  
Pins  
Function  
OE  
Output Enable Input  
LE  
D0–D7  
O0–O7  
Latch Enable Input  
Data Inputs  
3–State Latch Outputs  
1
2
3
4
5
6
7
9
8
10  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
GND  
11/96  
Motorola, Inc. 1996  
REV 3  

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