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MC74LCX543SD PDF预览

MC74LCX543SD

更新时间： 2024-09-13 20:03:39
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
42页 360K
描述
LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24

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MC74LCX543SD 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：PLASTIC, SSOP-24
针数：24Reach Compliance Code：not_compliant
风险等级：5.56Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：8.2 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP24,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：225
电源：3.3 VProp。Delay @ Nom-Sup：7 ns
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：5.3 mmBase Number Matches：1

MC74LCX543SD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX543 is a high performance, non–inverting octal latching  
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
performance. A V specification of 5.5V allows MC74LCX543 inputs to be  
safely driven from 5V devices. The MC74LCX543 is suitable for memory  
address driving and all TTL level bus oriented transceiver applications.  
LOW–VOLTAGE CMOS  
OCTAL LATCHING  
TRANSCEIVER  
I
For data flow from A to B with the EAB LOW, the A–to–B Output  
Enable (OEAB) must be LOW in order to enable data to the B bus, as  
indicated in the Function Table. With EAB LOW, a LOW signal on the  
A–to–B Latch Enable (LEAB) input makes the A–to–B latches  
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal  
will latch the A latches, and the outputs no longer change with the A  
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are  
active and reflect the data present at the output of the A latches. Control  
of data flow from B to A is symetric to that above, but uses the EBA,  
LEBA, and OEBA inputs.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751E–04  
24  
1
SD SUFFIX  
PLASTIC SSOP  
• Designed for 2.7 to 3.6V V  
CC  
Operation  
24  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
CASE 940D–03  
1
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
• LVTTL Compatible  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948H–01  
• LVCMOS Compatible  
24  
• 24mA Balanced Output Sink and Source Capability  
1
• Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds 500mA  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
PIN NAMES  
Pins  
Pinout: 24–Lead Package (Top View)  
Function  
OExx  
Exx  
LExx  
A0–A7  
B0–B7  
Output Enable Inputs  
Enable Inputs  
Latch Enable Inputs  
3–State Inputs/Outputs  
3–State Inputs/Outputs  
V
EBA B0 B1 B2 B3 B4  
B5 B6  
16  
B7 LEAB OEAB  
CC  
24  
23  
22  
21  
20  
19  
18  
14  
17  
15  
13  
1
2
3
4
5
6
7
9
A5 A6  
11  
8
10  
12  
LEBA OEBA A0 A1 A2 A3 A4  
A7 EAB GND  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/96  
REV 0.3  
116  
Motorola, Inc. 1996  
1234567...42

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