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MC74LCX543DW

更新时间： 2024-09-12 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 159K
描述
LOW-VOLTAGE CMOS OCTAL LATCHING TRANSCEIVER

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中文翻译

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MC74LCX543DW 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP24,.4Reach Compliance Code：unknown
风险等级：5.92其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：7 ns传播延迟（tpd）：9.5 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

MC74LCX543DW 数据手册

 浏览型号MC74LCX543DW的Datasheet PDF文件第2页浏览型号MC74LCX543DW的Datasheet PDF文件第3页浏览型号MC74LCX543DW的Datasheet PDF文件第4页浏览型号MC74LCX543DW的Datasheet PDF文件第5页浏览型号MC74LCX543DW的Datasheet PDF文件第6页浏览型号MC74LCX543DW的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX543 is a high performance, non–inverting octal latching  
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
performance. A V specification of 5.5V allows MC74LCX543 inputs to be  
safely driven from 5V devices. The MC74LCX543 is suitable for memory  
address driving and all TTL level bus oriented transceiver applications.  
LOW–VOLTAGE CMOS  
OCTAL LATCHING  
TRANSCEIVER  
I
For data flow from A to B with the EAB LOW, the A–to–B Output  
Enable (OEAB) must be LOW in order to enable data to the B bus, as  
indicated in the Function Table. With EAB LOW, a LOW signal on the  
A–to–B Latch Enable (LEAB) input makes the A–to–B latches  
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal  
will latch the A latches, and the outputs no longer change with the A  
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are  
active and reflect the data present at the output of the A latches. Control  
of data flow from B to A is symetric to that above, but uses the EBA,  
LEBA, and OEBA inputs.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751E–04  
24  
1
SD SUFFIX  
PLASTIC SSOP  
• Designed for 2.7 to 3.6V V  
CC  
Operation  
24  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
CASE 940D–03  
1
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
• LVTTL Compatible  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948H–01  
• LVCMOS Compatible  
24  
• 24mA Balanced Output Sink and Source Capability  
1
• Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds 500mA  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
PIN NAMES  
Pins  
Pinout: 24–Lead Package (Top View)  
Function  
OExx  
Exx  
LExx  
A0–A7  
B0–B7  
Output Enable Inputs  
Enable Inputs  
Latch Enable Inputs  
3–State Inputs/Outputs  
3–State Inputs/Outputs  
V
EBA B0  
23 22  
B1  
21  
B2  
20  
B3  
19  
B4  
18  
B5  
17  
B6  
16  
B7 LEAB OEAB  
CC  
24  
14  
15  
13  
1
2
3
4
5
6
7
9
11  
8
10  
12  
LEBA OEBA A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7 EAB GND  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/96  
REV 0.3  
Motorola, Inc. 1996  
1234567...9

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