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MC74LCX543 PDF预览

MC74LCX543

更新时间: 2024-09-12 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
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9页 159K
描述
LOW-VOLTAGE CMOS OCTAL LATCHING TRANSCEIVER

MC74LCX543 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX543 is a high performance, non–inverting octal latching  
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
performance. A V specification of 5.5V allows MC74LCX543 inputs to be  
safely driven from 5V devices. The MC74LCX543 is suitable for memory  
address driving and all TTL level bus oriented transceiver applications.  
LOW–VOLTAGE CMOS  
OCTAL LATCHING  
TRANSCEIVER  
I
For data flow from A to B with the EAB LOW, the A–to–B Output  
Enable (OEAB) must be LOW in order to enable data to the B bus, as  
indicated in the Function Table. With EAB LOW, a LOW signal on the  
A–to–B Latch Enable (LEAB) input makes the A–to–B latches  
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal  
will latch the A latches, and the outputs no longer change with the A  
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are  
active and reflect the data present at the output of the A latches. Control  
of data flow from B to A is symetric to that above, but uses the EBA,  
LEBA, and OEBA inputs.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751E–04  
24  
1
SD SUFFIX  
PLASTIC SSOP  
Designed for 2.7 to 3.6V V  
CC  
Operation  
24  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
CASE 940D–03  
1
I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
LVTTL Compatible  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948H–01  
LVCMOS Compatible  
24  
24mA Balanced Output Sink and Source Capability  
1
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
PIN NAMES  
Pins  
Pinout: 24–Lead Package (Top View)  
Function  
OExx  
Exx  
LExx  
A0–A7  
B0–B7  
Output Enable Inputs  
Enable Inputs  
Latch Enable Inputs  
3–State Inputs/Outputs  
3–State Inputs/Outputs  
V
EBA B0  
23 22  
B1  
21  
B2  
20  
B3  
19  
B4  
18  
B5  
17  
B6  
16  
B7 LEAB OEAB  
CC  
24  
14  
15  
13  
1
2
3
4
5
6
7
9
11  
8
10  
12  
LEBA OEBA A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7 EAB GND  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/96  
REV 0.3  
Motorola, Inc. 1996  

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