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MC74LCX373 PDF预览

MC74LCX373

更新时间: 2024-11-04 22:12:47
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 162K
描述
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MC74LCX373 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX373 is a high performance, non–inverting octal  
transparent latch operating from a 2.7 to 3.6V supply. High impedance  
TTL compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE  
CMOS OCTAL  
TRANSPARENT LATCH  
performance. A V specification of 5.5V allows MC74LCX373 inputs to be  
I
safely driven from 5V devices.  
The MC74LCX373 contains 8 D–type latches with 3–state outputs.  
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters  
the latches. In this condition, the latches are transparent, i.e., a latch  
output will change state each time its D input changes. When LE is LOW,  
the latches store the information that was present on the D inputs a setup  
time preceding the HIGH–to–LOW transition of LE. The 3–state standard  
outputs are controlled by the Output Enable (OE) input. When OE is  
LOW, the standard outputs are enabled. When OE is HIGH, the standard  
outputs are in the high impedance state, but this does not interfere with  
new data entering into the latches.  
DW SUFFIX  
PLASTIC SOIC  
CASE 751D–04  
20  
1
M SUFFIX  
PLASTIC SOIC EIAJ  
Designed for 2.7 to 3.6V V  
CC  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
Operation  
20  
CASE 967–01  
1
I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
LVTTL Compatible  
SD SUFFIX  
PLASTIC SSOP  
CASE 940C–03  
20  
LVCMOS Compatible  
1
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948E–02  
Latchup Performance Exceeds 500mA  
20  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
1
Pinout: 20–Lead (Top View)  
PIN NAMES  
V
O7  
19  
D7  
18  
D6  
17  
O6  
16  
O5  
15  
D5  
14  
D4  
13  
O4  
12  
LE  
11  
Pins  
Function  
CC  
20  
OE  
Output Enable Input  
LE  
D0–D7  
O0–O7  
Latch Enable Input  
Data Inputs  
3–State Latch Outputs  
1
2
3
4
5
6
7
9
8
10  
OE  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
GND  
11/96  
Motorola, Inc. 1996  
REV 4  

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